LTspice transistor model issue

Question

I am importing a custom transistor model in LTspice. Simulating the family of curves for a single device works perfectly though adding another transistor causes the simulator to go incredibly slow and not finish.

For an example I am trying an NMOS inverter circuit, with a DC simulation varying the input gate voltage from -3 to 10VDC in 1V steps. If I hover over the top left of the window I can see text at the bottom reading: "Stepping source: 100% step size =2.95928e-005 N-R iterations: 39 fill-ins:0" while the text changes the iterations.

Here is the model I am using:

.MODEL PlanarFET NMOS 
 + LEVEL = 3 
 + L = 2E-06 
 + W = 1E-05 
 + UO = 9.67 
 + VTO = 1.5 
 + NFS = 0 
 + TOX = 3E-08 
 + NSUB = 1.616E+16 
 + NSS = 0 
 + VMAX = 2183 
 + RS = 4.441E-11 
 + RD = 3.09E+04 
 + RSH = 0.03236 
 + CBD = 0 
 + CBS = 0 
 + CJ = 0 
 + MJ = 0.5 
 + CJSW = 0 
 + MJSW = 0.33 
 + IS = 4.277E-08 
 + PB = 0.8 
 + FC = 0.5 
 + XJ = 0 
 + LD = 0 
 + DELTA = 0 
 + THETA = 0 
 + ETA = 0.4576 
 + KAPPA = 0.1077

L= 2u
W = 10u
AD = 9p 
AS = 9p
PD = 12u
PS = 12u

LTspice simulation file: https://easyupload.io/heso8u

I have tried with the default spice simulator settings, and also changing the setting without luck. Any suggestions?

In your second simulation, you left the body open. Was that intentional? — Hearth, Oct 21 '22 at 17:36
Whoops haha thanks good catch, I have been trying too many of these simulations to see if I can get something to work. However grounding the body/substrate here does not many any difference. — Barlo67, Oct 21 '22 at 17:51
For clarity, updated with LTspice file properly grounded and updated pic. — Barlo67, Oct 21 '22 at 17:54
@Barlo67 You have a node without a galvanic connection (between the two FETs.) Stick something there, like a 10 MegOhm resistor to ground. See if that helps. I think it is struggling over that node. — jonk, Oct 21 '22 at 18:15
@jonk thanks for the input, basically then putting a 10M ohm resistor from the output to ground. Doing so gets it to work, but I also get 380nA of current through that resistor to ground which isn't good. Increasing the resistance further or seemingly messing with the supply voltages also seems to re-cause that original error. This also doesn't happen at all with the default LTspice transistor model. — Barlo67, Oct 21 '22 at 18:30
@Barlo67 In that case I think you may need to read the help on MOSFETs, first, and then carefully look over your model description comparing each of them to each found in the Help. You may spot something important doing that. I usually refer to the standard BSIM models and modify those, though. — jonk, Oct 21 '22 at 18:42
@Barlo67 Is your FET meant to be supplied with 7 V and gate at 9 V (V2 does not change through the .DC card)? Try adding some series resistances, even 1 Ω. Or try the alternate solver, that seems to work. — a concerned citizen, Oct 21 '22 at 19:12
@aconcernedcitizen Yes for the NMOS putting that voltage on the gate is having it on all the time, treating it like a resistor, but woo :D putting a bunch of 1ohm resistors everywhere and using the alternative solver seemed to have fixed it! Thanks for the help! — Barlo67, Oct 21 '22 at 19:38
@Barlo67 Interesting, that. Mike recommended (decades ago) to use a current source and a 1 Ohm resistor (or like that) in parallel instead of using voltage sources. The solver prefers it. — jonk, Oct 21 '22 at 23:46
@jonk It's mainly because current sources don't grow the MNA conductance matrix, while voltage sources do. You can look at the SPICE Error Log (CTRL-L) after a simulation to inspect the "matrix size". Replace a voltage source with a current source and the size will go down. Interesting reference here if you're curious: https://qucs.sourceforge.net/tech/node14.html — Ste Kulov, Oct 23 '22 at 03:53
@Barlo67 Your family of curves looks good now. How did you fix the IC-CAP/LTspice discrepancy issue you had before? You can answer your own [previous question](https://electronics.stackexchange.com/questions/638619/why-does-ic-cap-spice-level-3-mosfet-not-match-in-ltspice) with whatever you did to solve your issue so it could help others in the future. (plus I'm curious) — Ste Kulov, Oct 23 '22 at 04:01

score 2 · Accepted Answer · answered Oct 22 '22 at 06:57

First, it will do you good to draw more readable schematics -- but also for the rest of us, trying to read it, peacefully.

Then, the level=1,2,3 MOSFETs are really old models from the 80s, level=1 dating back to the original SPICE, some 50 years ago. And they have their own problems, one of them being rather stiff and not very friendly, derivative-wise. They will work but, trying to build on them may fail, from time to time. As @jonk notes in the comments, the BSIM models (level=8 and above, see the help under LTspice > Circuit Elements > M. MOSFET) are better behaved and sometimes it pays to allocate a few more minutes to convert the parameters.

To help with convergence, Mike (the creator of the program) said that it is better to use current sources terminated into appropriate resistors (also see the help under LTspice > Circuit Elements > E. ..., last paragraph), or adding some series resistance to the stiff voltage sources. For this case, however, the alternate solver is enough. It's meant to be about 1000x more precise than the normal solver but, at some 2x slower speeds. It depends, though: for some circuits it's actually faster but, then, those circuits would have crawled under the normal solver. When in doubt, try it, that's why the option is there. Most often than not, the alternate solver will get you over many glitches.

LTspice transistor model issue

1 Answers1