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I've often heard that trench MOSFETs have a narrower FBSOA than planar MOSFETs due to their cell design. The explanation I've commonly seen is that the cell design has a negative Rds(on) temperature coefficient, so if a single cell gets warmer than the others it has a tendency to receive a greater proportion of the current and go into thermal runaway. I've heard this referred to as the Spirito effect in the context of operating MOSFETs in a linear manner.

The implication appears to be that the runaway behaviour arises from the trench MOSFET being constructed from lots of smaller MOSFET "cells" in parallel. However, given descriptions I've seen of planar MOSFET construction, they don't seem to be constructed from one single monolithic cell. The literature refers to planar MOSFETs as having gates, plural, in practice. It isn't clear to me why there is such a distinction between the two from a thermal runaway perspective.

I've also read that the narrow FBSOA of trench MOSFETs is in part due to the lower Rds(on) causing a "higher point of intersection between two transfer curves at different temperatures". This was sourced to "Improved SOA analysis for trench MOSFETs using the Spirito approach" by Kwan et. al., but I was unable to find the original material being referenced. This statement is unclear to me. My rough intuition is that this is about a current equilibrium between cells not being reached until a higher temperature, but it feels a bit vague.

Could someone shed some light on this? What aspect(s) of the trench construction cause this difference in thermal runaway behaviour? Why are planar MOSFETs considered more immune to these behaviours? And what is meant by the higher point of intersection between the transfer curves?

Polynomial
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  • Note, Rds(on) has a positive tempco; you're talking about the linear mode operation, which roughly speaking has to do with the negative Vgs(th) tempco. – Tim Williams Oct 17 '22 at 01:42
  • Ah, yes, sorry, you're right - I was confusing the Rds(on) tempco and the Vgs(th) tempco. – Polynomial Oct 17 '22 at 02:27

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All power MOSFETs are constructed from smaller cells in parallel.

Trench FETs are 'better' than lateral ones because they have less parasitic series resistance (in the drain). Thermal runaway can occur when the negative VTH threshold has a stronger effect than the positive drain resistance (and channel resistance) effects. This generally requires VGS just a bit above threshold on the device (if it is >> threshold there is just a simple high power problem). Runaway also requires that the thermal coupling between regions is less than the differential power increase from differential temperature increase - this is much worse at higher VDS.

jp314
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  • So what you're saying is that in trench FETs the magnitude of the Vgs(th) tempco is typically larger than the parasitic drain resistance? Could you explain why the relative magnitude of the parasitic drain resistance is relevant here? I'm also still unclear on the intersection point. – Polynomial Oct 17 '22 at 02:30
  • It's basically d(ID)/dT generating d(power), and if the local thermal resistance is too high they generates dT. If that > 1, you get runaway. At low VDS (in triode) drain resistance matters. At high VDS, not so much – jp314 Oct 17 '22 at 02:55
  • I understand the mechanism behind the individual cell runaway, I'm just confused as to why trench experiences that effect more heavily than planar constructions. Are you saying that the higher parasitic drain resistance in a planar FET acts to reduce transconductance, and therefore reduces the increase in Ids as a function of Vgs, which in turn reduces the overall effect of the negative Vgs(th) tempco? – Polynomial Oct 17 '22 at 03:19
  • Yes -- although this is only apparent when VDS is low enough that drain resistance affects the current flowing. in that case, VDS is reasonably low, so thermal runaway isn't as likely anyway. – jp314 Oct 17 '22 at 04:44
  • That leaves me even more confused. If the impact of the planar FET's drain resistance is only apparent at low Vds and low current, why is it responsible for the difference in FBSOA, the relevance of which is usually characterised by _high_ Vds? – Polynomial Oct 17 '22 at 21:12