How to write to a Hitachi HM628128A SRAM?

Question

I'm working with a Hitachi HM628128A SRAM chip.

According with the datasheet, the function table is

How do I write data in the chip? Must I execute "write cycle (1)" and then "write cycle (2)", or can I just choose one of the two methods?

Answer 1

You can use either method, the two different timing diagrams in the document illustrate two different timing schemes that can be used for a write operation. My guess is they do this to facilitate different controllers or to maintain compatibility with other IC's

Answer 2

You can use either one, whichever fits with your system doing the write.

Answer 3

From HM628128A Series - 131,072-word × 8-bit High Speed CMOS Static RAM

1. A write occurs during the overlap of a low \$\overline {CS1}\$, a high CS2, and a low \$\overline {WE}\$. A write begins at the latest transition among \$\overline {CS1}\$ going low, CS2 going high, and \$\overline {WE}\$ going low. A write ends at the earliest transition among \$\overline {CS1}\$ going high, CS2 going low, and \$\overline {WE}\$ going high. \$t_{WP}\$ is measured from the beginning of write to the end of write.

11. In the write cycle with \$\overline {OE}\$ low fixed, \$t_{WP}\$ must satisfy the following equation to avoid a problem of data bus contention. \$t_{WP}\$ ≥ \$t_{DW}\$ min + \$t_{WHZ}\$ max

So \$\overline {OE}\$ can be tied low. And one pin \$\overline {WE}\$ can function as a Read (High) and a Write (Low). Or \$\overline {WE}\$ can be used for writes and \$\overline {OE}\$ used for reads.

One Read/Write line or separate read/write lines.

But if \$\overline {CS1}\$ is low and CS2 is high, the hard tied \$\overline {OE}\$ means the SRAM will be driving the data bus which could result in data corruption on a write with the processor. As in watch the timing, because \$\overline {OE}\$ is tied active.