I have a question regarding the standard cell design flow in an ASIC design flow.
That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured design flow directly follows, which basically means that the lithographic layers include specialized design blocks like memories, controllers, PLLs and others. In some sense they are also tidily coupled with an FPGA since FPGAs also often incorporate some predefined blocks like memories, PLLs and so on.
On the other side of the spectrum there is the full custom design flow where the designer needs to specify the placing of every single transistor of the device. This means that all lithographic layers need to be customized for a full custom design.
Somewhere in between there is the standard cell design flow. I do understand that a standard cell basically encapsulates the functionality of a specific gate or cell. We can have cells that implement an AND gate, an OR gate, or even something like a full adder, PLL, or a flip-flop.
But even with a standard cell design flow the foundry would still need to create all the lithographic layers for the design. Otherwise it wouldn't really differ from a gate array design flow. If the foundries actually need to manufacture every layer where does the benefit of a standard cell design stand beside the obvious simpler design flow and lesser risks in the implementation?
Is the standard cell design flow basically a full custom design flow but with predefined cells? If not what are the differences? I could imagine that the manufacturing process of the lithographic layers for a standard cell design could be easier for the foundry since their production pipelines already are configured for their standard cells. However I fail to find any information that would confirm my speculations.
What I try to understand is how a standard cell design flow differs from a full custom one from the manufacturing perspective. I would also appreciate any sources that would clarify this topic.
