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I am making a deadtime circuit proposed by Verbal Kint and I ran into an issue where the AND gate I'm using is only giving logic level signals.

Is there an AND gate buffer anyone could recommend to make the output a suitable voltage where it can be fed into a gate driver for a half bridge inverter?

enter image description here

ocrdu
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Joshua Oconnell
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    Are you implying that you have chosen a gate driver that does not have logic-level inputs? – CL. Sep 03 '22 at 17:45
  • @CL. That is a good question. For some reason I thought it would require a voltage higher than 1V to be recognized it's respective pin on the driver. On the datasheet it's Absolute Maximum Rating for both PWM-Hi and PWM-Low is [0, 20]. Does that mean this logic level input will suffice? – Joshua Oconnell Sep 03 '22 at 17:51
  • Is there a reason why you are using TTL parts instead of CMOS. These parts are available in the "AC" or "HC" series. 74AC08, etc. CMOS is better in almost every way. – Mattman944 Sep 03 '22 at 18:21
  • If you only have TTL add a pull down of <=470 to the filtered input. – Tony Stewart EE75 Sep 03 '22 at 21:59
  • For TTL you can make something work in the lab if the TTL input can swing above/below 2 diode drops. That is the real threshold. The rated levels 0.8, 2V are for noise immunity. – Tony Stewart EE75 Sep 04 '22 at 01:30
  • @JoshuaOconnell You mean something like a transistor buffer sage (e.g. NPN-PNP pair)? – a concerned citizen Sep 04 '22 at 07:06
  • The absolute maximum rating does not tell you what voltage is read as high; see the electrical characteristics. There are gate drivers (e.g., UCC27517) that advertize TTL-compatible inputs. – CL. Sep 04 '22 at 09:45

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2 problems : TTL and logic inversion

I see you are using two AND gates when he indicated one AND for positive logic output = ON low side Nch then OR for negative logic high side Pch.

But if you are using dual Nch half Bridge with PWM low side to Boost Vs on high side then you may want positive logic for both.

Then you need to invert the top side to a NOR with AND on the low side.

Using de Morgan's Law there are many other variations. The only problem with Andy's XOR gate is the prop delays at high speeds (> 1MHz) are unequal for tHL and tLH.

Falstad Sim

Due to source current TTL does not work for this method using high resistor values for active low.

It is designed for CMOS logic which is prone to +/-33% tolerance on the threshold between devices and all temperatures and thus must be taken into consideration. CMOS source impedance is defined by Vol/Iol {typ, max} and change with each family from HC to AC but range 66 to 22 Ohms unless CD4xxx HV logic family was used. Schmitt triggers are prone to the same threshold tolerances. Thus high values of R and small values of C are practical as input impedance > 10M and < 5pF roughly.

enter image description here

Middle plot show both combined to for easy display of overlap.

The concept is slow turn ON and fast turn OFF to create the deadtime signals.

Tony Stewart EE75
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