Would having multiple LDOs with different output voltages are in series, for example: 5 V from a buck converter -> LDO1 (3.3 V) -> LDO2 (2.8 V), and assuming all LDOs satisfy the dropout voltage requirement, provide better power supply rejection ratio (PSRR) compared to the configuration without LDO1 (so 5V to 2.8V directly)?
Does the PSRR of the LDOs in series (at the same frequency) sum up?
Yes, the PSRRs of the two LDOs in series will sum up. As you pointed out, you have to check the PSRR vs. frequency of each LDO, and then you should be able to sum the rejection in dB of each LDO to arrive at the overall PSRR for the series combination.
Another thing to keep in mind since you mentioned drop-out is that PSRR is specified with a specific voltage headroom across the LDO, which may be substantially larger than the drop-out rating, and as you approach drop-out from that value, the PSRR will degrade:
From the TPS7A20 datasheet, as en example:
Yes, PSRRs will stack, but... this is a LDO:
Dropout voltage is the pass MOSFET's Vds. When Vds gets low, the MOSFET's transconductance drops and its capacitance increases, which means it gets slower, the control loop loses both bandwidth and gain, and PSRR drops significantly. When a LDO reaches its specified dropout voltage, the FET is fully on, and PSRR is zero.
Datasheet PSRR is specified for a value of Vin-Vout which is mentioned, and actual PSRR in your application will be lower if Vin-Vout gets close to the minimum dropout voltage. If the manufacturer is honest, they will put PSRR plots with a realistic dropout voltage that corresponds to the most common application.
So there is a compromise, if you don't have much margin between input and output, one LDO may actually have better PSRR that two LDOs in series. But if each LDO has enough Vin-Vout to work, then two in series will offer much better PSRR.
