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I have the idea that the design constrains we use at our company are a little to strict. No one can tell me where the values come from.

According to the MIPI standard the inter-Lane Skew for signals equal to or lower than 1.5[Gbps] should be less than UI/50, where UI is half the clock period.

The data rate of my new design will be 600[Mbit/s] divided over 4 lanes, so 150[Mbit/s] Like DDR, MIPI data is clocked on the rising and falling edge, so the frequency will be half the data rate. 150[Mbit/s] = 75[MHz]

My calculation for skew: UI = (1/f)(1/2)= (T)(1/2) = (1.310^-8)/2 = 6.6610^-9 ###T=1/f skew = UI/50 = (6.6610^-9)/50 = 1.3310^-10[s] = 0.133[ns]

If we calculate with a speed of 150[mm/ns] This means that the inter lane skew in distance well be 150[mm/ns]*0.133[ns] = 20[mm] So between clock and data lane a difference of 20[mm] is allowed, which I think is a lot.

However, in other designs that we made we have a restriction of 0.002[ns] so 0.09[mm] In these designs the frequency is indeed higher, let's say ten times.

If we would divide the calculated 20[mm] by 10 we get 2[mm] this is still 10 times bigger then the constraint of 0.09[mm].

What do you think. Is the 0.09[mm] or 0.002[ns] taking it to far or a well considered constraint?

Dukel
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  • What if the skew limit is not due to data rate but for completely other reasons? Can you think of any other reason in addition to data rate why skew must be within some tighter limits, even if MIPI allows very sloppy timings due to it's internal operation? – Justme Sep 02 '22 at 16:45
  • Skew also leads to an imbalance in return current which can be an EMI issue. – hacktastical Sep 02 '22 at 17:09
  • I wonder how skew affects the CMRR of crosstalk becomes more frequency selective. But then a 1 ps budget for 400 MHz is only 0.2 um is achievable if all else is matched like pad pF and current – Tony Stewart EE75 Sep 02 '22 at 17:41
  • I too wonder about the discrepancy in the skew timing budgets, but I have to assume that TI, TEK, INTEL, NXP, must have had good reasons. Now what was the main reason? – Tony Stewart EE75 Sep 02 '22 at 17:58
  • @Justme, as far as I know this requirement is coming only front he skew. – Dukel Sep 03 '22 at 16:27
  • @TonyStewartEE75, what do you mean with "What was the main reason"? The main reason for the length matching requirement is the MIPI skew spec – Dukel Sep 03 '22 at 16:31
  • The margin for fixed cluster of eye patterns has a budget for BER. some margins are static like skew delay while there is also a spectrum emission of common mode noise due to skew that changes with time delay and transition rate. As etching tolerances and design choices for routing become tighter with increasing speed, I suspect for example a 1ps or a 0.1 ps skew is easier to control than the tolerances of components on trace impedance, mismatch, load capacitance, and differential attenuation rise with jitter from ISI when rising data rates have steeper slopes for dB / octave from 6 to ~20 . – Tony Stewart EE75 Sep 03 '22 at 17:55

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