This is a more theoretical question.
Is it possible to use internal building blocks of an Ethernet PHY directly and without typical Ethernet framing?
I am looking for a way to have access to the internal PAM/PCS structures (twisted pair) to use it with a (best case) continuous data stream (i.e. 100Base-T). Especially I want to get rid of preamble and interpacket-gap.
Is this possible?
Are there any PHY's which can be set into that kind of mode?
Unlikely, because it's not meant for streams as it is meant for packets.
100Base-TX receiver synchronizes the scrambler to the receives symbols by using the IDLE symbols sent between packets. An example PHY requires 12 IDLE symbols to synchronize. So likely it does not synchronize if there is no IDLE symbols. It may be possible to bypass the scrambler.
But if there are no packets sent but just continuous stream of data, there is never start-of-packet symbols received and thus the receiving side cannot determine how to align the received 5-bit symbols, because there is no IDLE symbols that would follow with start-of-packet symbols. So the PHY would never signal that received data is valid and PHY would not output data.
Even if you did manage to synchronize the devices by sending IDLE and single start-of-packet before starting transmission of infinitely long stream, any glitch would make the devices loose synchronization or symbol alignment.
And you would have to use MII interface because it outputs the actual recovered data clock. RMII interface uses elastic receive buffers so that local reference clock can be used to transfer received data, so the FIFO would eventually underrun or overrun when sending a too long packet.
