A NMOS gate controls when the clock signal is fed into the clock of the D flip-flop.
Below is the NMOS gate schematic and simulation. As we can see, the Vsquare only goes through the NMOS when the gate voltage Vstep2 is high. No problem!
But if I connect this clock signal to the D flip-flop, it gives me a simulation error at 50 nm.
Now the tricky thing is that if I give the D flip-flop the clock signal directly without the NMOS gate, the simulation works fine without any error.
Does anyone know how I can make some tweak to avoid the simulation error when sending the clock signal to the D flip-flop through an NMOS gate?
