Expected behavior:
In hardware I connect UART of a number 0/1
to the correct pin numbers TX/RX
and get it based on that connection
Actual behavior:
In hardware I connect UART of a number 0/1
to the correct pin numbers TX/RX
and got it on all of the related UARTs 0/1
.
I have this array of UARTs where I can split them like USB ports, and when I receive an input I get it from different indices.
To me it's a bit strange but it gets on all UART0
at once even though I'm connecting a certain one only, or the same on all UART1
.
ports = [
UART(0, 115200, timeout=0, tx=Pin(0), rx=Pin(1)),
UART(1, 115200, timeout=0, tx=Pin(4), rx=Pin(5)),
UART(1, 115200, timeout=0, tx=Pin(8), rx=Pin(9)),
UART(0, 115200, timeout=0, tx=Pin(12), rx=Pin(13)),
UART(0, 115200, timeout=0, tx=Pin(16), rx=Pin(17))
]
The code:
from machine import UART, Pin
from time import time
import re
ports = [
UART(0, 115200, timeout=0, tx=Pin(0), rx=Pin(1)),
UART(1, 115200, timeout=0, tx=Pin(4), rx=Pin(5)),
UART(1, 115200, timeout=0, tx=Pin(8), rx=Pin(9)),
UART(0, 115200, timeout=0, tx=Pin(12), rx=Pin(13)),
UART(0, 115200, timeout=0, tx=Pin(16), rx=Pin(17))
]
def read_ports():
"""Returns a list of ports with indecies that are receiving data"""
port_list = []
for i,port in enumerate(ports):
if port.any() > 0:
port_list.append({
"port": port, "index": i
})
return port_list
request = [
bytes(),
bytes(),
bytes(),
bytes(),
bytes()
]
while True:
# Available Ports
active_ports = read_ports()
if len(active_ports) == 0:
continue
for uart in active_ports:
index, port = uart["index"], uart["port"]
byte = port.read(1)
if byte == b'' or None or not byte:
continue
print("(index %d) (length %d) byte" % (index, len(request[index])), byte)
request[index] += byte
If I have UART0 connected all UART0s get the bytes at random.
I just don't get it; why? And how to solve it?
And if it's normal behavior what is the point of having all of these UART ports if I can't use one when I need many?