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According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)? If not, are traces ("litmus tests") like the following possible, where core1's MMIO read operation, core 2's remap and subsequent MMIO read operations cannot be liearlized?

  1. core1 resolves address ADDR1 to DEV1 as the first part of the operation "LOAD ADDR1 into reg1"

  2. core2 remaps DEV1 from ADDR1 to ADDR2

  3. core2 resolves address ADDR2 to DEV1 as the first part of the operation "LOAD ADDR2 into reg1"

  4. core2 reads value 5 from DEV1 as the final part of the operation "LOAD ADDR1 into reg1"

  5. core1 reads value 6 from DEV1 as the final part of the operation "LOAD ADDR2 into reg1"

Suppose DEV1 is a timer which returns the current count. So from the trace, it is clear that core2's MMIOread got to DEV1 before before core1's MMIOread, yet, core1's address resolution part of MMIOread must have happened before core2's remap operation.

winny
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Abhishek Anand
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    The PCI(e) specs describe a single bus, where all accesses a linearizable because they are linearized. A remapping happens either in virtual address space (which does not affect the bus), or by reconfiguring the PCIe device (which also is a PCI(e) transaction). – CL. Aug 25 '22 at 10:32
  • If I remember correctly, you also need to disable address decoding to alter the BARs. – Simon Richter Aug 26 '22 at 21:08

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