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I've been reading through the 802.3 standards recently and am learning about alignment markers inserted as blocks in ethernet frames to deskew PCS channels.

While I can find information about the bit-by-bit content of these alignment markets, how would physical circuitry at the receiver use these bits to correct for skew? Is there some kind of digital feedback loop and delay circuitry involved as is seen in the clock recovery PLL?

Dragonsheep
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    Possibly a shift register with adjustable tap – user253751 Aug 17 '22 at 13:01
  • If it's just these kinds of small adjustments, doesn't clock recovery already provide synchronization within the whole block? I'm not sure if I follow why there's need for deskew on top of this. – Dragonsheep Aug 18 '22 at 11:34
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    symbols from different lanes presumably need to be aligned with each other. It's 1 network connection using 4 pairs, not 4 separate network connections. If the symbols on a pair come early they need to be delayed to match up with the symbols on the other pairs – user253751 Aug 18 '22 at 13:01

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