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Assume that within an FPGA, I have two data streams that are being driven by two clocks. The two clocks are generated by 2 physically separated PLLs (still within the same FPGA), both of which have the same single input reference oscillator, and both PLLs are setup identically in terms of parameters.

I now want to combine both streams of data and feed to a single logic block with a single clock. Assume after the PLLs are locked, do I need to perform a clock crossing operation, or since both PLLs are the same within some tolerance, Can I just grab one of the clocks and use all signals directly?

Sittin Hawk
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  • As ever, It depends. What is the relationship between the oscillator frequency and the data bus frequency? (same freq? higher freq? lower freq?) – Tom Carpenter Aug 11 '22 at 18:45
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    PLLs have jitter (well, all clock distribution schemes have jitter, but some more than others). Does the jitter tolerance allow you to combine the streams without violating the receiver's setup and hold requirements? If yes, then yes, just grab one clock. If no, then you need to do something else. Change your design to increase jitter tolerance, or implement clock domain crossing circuits. – Neil_UK Aug 11 '22 at 18:57
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    I had to do something like that recently -- I needed to combine the outputs of four high-speed serial-output ADC chips into a single stream of words. Each ADC was given the same reference clock, but the data came back with its own clock with a fairly arbitrary phase relationship. I was able to determine that after deserialization, the total variation in phase at the word clock rate was small enough that a simple register sufficed to align the four channels. You will have to do a similar analysis for your situation. Setting up the timing constraints correctly becomes rather "interesting". – Dave Tweed Aug 11 '22 at 19:34
  • @DaveTweed Okay thanks. I wasn't sure if the timing tools typically did this automatically or if it's something you need to write timing constraints for. – Sittin Hawk Aug 11 '22 at 20:54
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    ... Why not clock both data stream generators with the same PLL? – user253751 Aug 11 '22 at 23:08
  • @user253751 I would if I could. – Sittin Hawk Aug 12 '22 at 13:28
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    Why can't you ? – user253751 Aug 15 '22 at 19:36
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    Technically, they are two asynchronous clock domains even if the frequencies / phase shift are same. Because, they can have jitter variations which are independent to each other. But as Neil said, if jitters are tolerable to meet setup/hold (especially if larger frequencies), you can analyse this path using STA or manually and take a decision to use one of the clocks or put an Async FIFO. But I wonder why you need two clocks at all for your requirement? – Mitu Raj Aug 17 '22 at 09:45

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