The CPU in your link is a soft CPU, from an FPGA/CPLD perspective. The Verilog HDL source files carry the digital logic circuit design for the CPU.
The CPU is just one part of a microprocessor, which is just one part of a microprocessor system. So you'd need more HDL that carries all of that digital logic circuit. That can be simulated, debugged, then synthesized to produce a configuration file for an FPGA. You may find that on the Internet, already done by someone - that'd be something for you to track down yourself.
Once that's in an FPGA, you could then write assembly language programs or compile an HLL for it, depending on the software tools available.
The Verilog could target an ASIC but I imagine that's well beyond what's available to you.