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What I am reading has this circuit:

enter image description here

It also has this description:

In analog power on reset implementation, the time and voltage threshold factors are characteristic of an analog circuit. The time period of the reset state is determined and measured using the charging of a capacitor which is placed in series with a resistor. When power is applied, the current goes via the capacitor and the voltage of capacitor increases slowly. At the beginning, the voltage is lower than the reset input pin threshold voltage and all elements in the CPU are hold in reset mode. And then, the voltage is higher than that threshold voltage, the reset pin gets a “1” and the system initializes. The values of the resistor and capacitor determine the power on reset latency.

I have some questions about this I hope you can help me with:

  1. Is it so that the voltage at the reset signal in the start will be ground, but after a while it will be VCC?

  2. If we get that the voltage after a while at the reset signal is VCC is there a voltage drop over the resistor? From what I understand there can be no voltage drop over resistors if there is no current?

user394334
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2 Answers2

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The way that is drawn, when the system is first powered up, the Reset pin will be pulled up to VCC. The capacitor has no charge on it, so the voltage across it is zero.

As the capacitor charges, the voltage across it increases, the voltage across the resistor decreases, and the voltage on the Reset pin drops towards Ground.

If that's the wrong way round for what you want, swap the capacitor and resistor over.

Simon B
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  • Thank you, unfortunately I can only accept one answer. – user394334 Aug 05 '22 at 20:37
  • @user394334 This answer, however, has an important point about swapping components to get correct voltage for !RESET inputs, used by many, if not all chips. – Maple Aug 05 '22 at 20:45
  • @Maple Thank you. Is it correct that you mean that we want the reset signal to be Ground at the start and VCC after a while, becasue components will be reset when the reset signal is Ground? – user394334 Aug 05 '22 at 21:11
  • @user394334 Yes, that is correct, assuming your particular device has !RESET input, the "!" sign or horizontal line above "RESET" denoting active-zero logic. If your device has active-high reset logic then your schematics is OK. – Maple Aug 05 '22 at 22:07
  • Yes, usually a !RESET means active low, where a logic LOW asserts the reset. The part number of the CPU is not given, but I don't think I have ever seen a device where a logic HIGH asserts the reset. – PStechPaul Aug 05 '22 at 22:37
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  1. No, it's the opposite, because capacitor starts empty, voltage at reset pin will be VCC, and when capacitor is charged fully, it will be GND.

  2. Assuming the inversion that happened in your explanation versus the picture is taken care of, and when capacitor is charged, there will be GND at reset pin, if no current flows out of reset pin.

Justme
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