What I am reading has this circuit:
It also has this description:
In analog power on reset implementation, the time and voltage threshold factors are characteristic of an analog circuit. The time period of the reset state is determined and measured using the charging of a capacitor which is placed in series with a resistor. When power is applied, the current goes via the capacitor and the voltage of capacitor increases slowly. At the beginning, the voltage is lower than the reset input pin threshold voltage and all elements in the CPU are hold in reset mode. And then, the voltage is higher than that threshold voltage, the reset pin gets a “1” and the system initializes. The values of the resistor and capacitor determine the power on reset latency.
I have some questions about this I hope you can help me with:
Is it so that the voltage at the reset signal in the start will be ground, but after a while it will be VCC?
If we get that the voltage after a while at the reset signal is VCC is there a voltage drop over the resistor? From what I understand there can be no voltage drop over resistors if there is no current?