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I am playing with a cascode op-amp design and I have problems judging its stability (schematic at the end of the post).

When I judge the DC or AC analyses, it all looks good. No peaking and good phase margin well beyond the unity gain point (~10 MHz ballpark).

However, in the time domain (.tran) analysis, the whole thing is oscillating, at about 1-10 MHz. Essentially, the current mirror is oscillating between fully on and fully off, with the current alternating between both input legs. I have tried changing several things, but the oscillation persists, only changes frequency slightly:

  • component values
  • inserting some .options such as cshunt or gmin
  • replacing the ideal elements with real elements
  • reducing the gain on the current mirror and on the level shifter M3
  • compensation capacitors
  • setting the input voltage source to zero constantly
  • replacing V4 with a current source and resistor

The only thing that remedied the oscillations in the time domain analysis, was to reduce abstol=1e-4. But as this is such a 'weak' convergence value, I think that it would rather mask issues instead of repair them.

Another remedy comes with the fix recommended by @James in comments, however, this seems to deteriorate the AC plots severely as seen below the schematic at the end.

Question

Does this mean that the below op-amp structure is by design not going to work? If so, why not?

If there is no fundamental flaw, do you have some suggestions what could be the issue?

enter image description here

AC plots before and after fix recommended by @James

The fix was to add a 100 pF miller cap to M3 and increase the closed loop gain to 10. The time domain sim becomes stable. But I would have thought, that the "fixed" version looks much worse in AC - with even negative phase at the point of 0 dB gain. Probably, the fix doesn't oscillate because the input bandwidth is restricted to before the danger zone by R5-C3.

BEFORE: enter image description here

AFTER: enter image description here

tobalt
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  • Read [this](https://www.analog.com/media/en/technical-documentation/lt-journal-article/ltjournal-v24n4-01-df-spicedifferentiation-mikeengelhardt.pdf) from Mike Engelhardt. It may help out. Voltage sources create problems in the matrix solver because of inverting 0 resistance. Current sources are superior for convergence, where possible. – jonk Aug 03 '22 at 11:53
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    Two things to try - 100pF comp cap from gate to drain of M3 and/or significantly increasing value of R14 to several kohms to increase the closed loop gain which reduces the loop gain. –  Aug 03 '22 at 11:54
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    @James Thanks! both taken together - a gain of 10 and 100pF miller cap - made it work. Hmm so it looks indeed like it is oscillating "in a normal way", i.e. by running out of phase margin while still having gain... Why would the AC analysis not show this. I will add a plot of the AC analysis – tobalt Aug 03 '22 at 11:57
  • Did you try setting the input source to 0 volts in the time domain analysis? – Andy aka Aug 03 '22 at 12:02
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    @Andyaka Just tried: oscillating. – tobalt Aug 03 '22 at 12:04
  • The graphs you added would be a lot clearer if they had the same vertical scale - why has the 2nd one suddenly got 20 dB more gain for instance? Does the input source have a DC offset possibly that is somehow different when performing an AC analysis? – Andy aka Aug 03 '22 at 12:08
  • However, the graphs are probably irrelevant to why LTSpice shows AC stable but transient unstable i.e. you are not looking to fix your circuit but to understand why? – Andy aka Aug 03 '22 at 12:14
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    @tobalt Ac analysis involves opening the loop (say at the inverting input), injecting a signal into the inverting input and measuring the gain and phase of the returned signal at the other side of the break whilst the non-inverting input is grounded. This can be difficult as the dc conditions across the break have to be catered for, this can be done with a large inductor (GH) connected across the break and injecting the test signal into the inverting input via a large capacitor. Are you just looking at the closed loop gain (input to output)? –  Aug 03 '22 at 12:20
  • @Andyaka The gain comes from increasing the closed-loop gain which was part of the fix. And yes, I am not really trying to fix up the circuit, but more to understand, why LTspice shows a stable AC and DC behavior, despite the circuit being unstable over a seemingly huge parameter space. – tobalt Aug 03 '22 at 12:25
  • @James I have also looked at all the intermediate nodes and I have seen no suspicious behavior there. The cascode and "cs" nodes follow the input up until the gain falls off. the input node to the level shifter follows with a little over 100x less of amplitude and 180° shift (as expected) and the input into the current mirror R2 has 0 amplitude at 0 Hz and rises steadily and peaks when the gain falls off at ~1/1000th of the input amplitude – tobalt Aug 03 '22 at 12:28
  • @tobalt What I'm asking is, are those plots of the loop gain as they should be or of the closed loop gain (input to output)? –  Aug 03 '22 at 12:32
  • @tobalt Perhaps you could read my last but one comment again. –  Aug 03 '22 at 12:41
  • @James I tried the AC method suggested before by you, and get more sensible results now, that show how your fix improves the phase margin! As the phase on the "far" side of the inductor is +90° shifted, how do I properly evaluate the phase margin ? Is it still the margin to -180° or is it actually the margin to -90° (being 180° below input) ? – tobalt Aug 03 '22 at 12:41
  • @James As it seems very likely that I was using the AC analysis wrongly (for the purpose to judge phase margin). It would be nice if you could illustrate what you said in comments as a short answer, so I can accept it . – tobalt Aug 03 '22 at 12:47
  • @tobalt When you open the loop, inject a signal and measure gain and phase at the other side of the break you are considering the whole loop including the inversion at the input summing junction and so the phase margin is how far short of -360 degrees the complete loop phase is when the complete loop gain is equal to 1. The large inductor is a short to dc thereby maintaining dc conditions but an open to ac thereby creating an ac break in the loop. –  Aug 03 '22 at 12:48
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    @tobalt You seem to have used "real" transistors, yet you are also using a VCVS (`E2`)? How do you intend to replace that? If you don't, then why not use a quasi-small-signal approach (e.g. simple `gm` current sources)? At any rate, if I replace `E2` with a [more palpable choice](https://i.stack.imgur.com/T3muk.png), it doesn't oscillate. – a concerned citizen Aug 03 '22 at 13:58
  • @aconcernedcitizen The `E` sources are placeholders for op-amps, as you suggest. I tried with opamps in other versions of this schematic (both UniversalOpamp as well as some "real" parts), but couldn't reproduce clean behavior. Might be a small part of the puzzle. But the major brick was that I was judging AC stability wrong. When I do it as suggested by James, the results agree with what I see in `.tran`. :) – tobalt Aug 03 '22 at 14:10
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    @tobalt In LTspice you can get rid of the huge L and C approach and use as you see in my screenshot. You can also use an input AC source (as you have it) and use the feedback resistor with `1 AC 1meg`, for example (that means for DC op point it will have 1 Ohm, and for the actual `.AC` analysis it will have 1 MOhm, effectively opening the loop). – a concerned citizen Aug 03 '22 at 14:14
  • Are you supposed to get away with using discrete power mosfets for monolithic IC design? Does anything change if you use [the monolithic models found here](http://cmosedu.com/cmos1/cmosedu_models.txt) and use it with the `nmos4` and `pmos4` symbols? Will have to set each transistor's W/L [according to the gains you need](https://www.researchgate.net/post/How-can-I-decide-the-W-L-ratio-of-MOSFET). – Ste Kulov Aug 03 '22 at 18:23
  • Don't know if this can help. Changed I2 from 6mA to 60uA. Gain is stable for R14>=3k with C1>=8pF. – Antonio51 Aug 19 '22 at 08:47

1 Answers1

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Just to close this off. User @James basically answered my issue in the comments (and @aconcernedcitizen refined the approach with respect to LTspice).

I did the AC analysis wrong with respect to judging phase margin/stability.

When done properly, I could easily see the lack of phase margin in the design and could fix it precisely with well known compensation techniques such as Miller RC around M3.

tobalt
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