Gate driver developing internal short

Question

In am trying to use a Texas Instruments DRV8300DRGER gate driver to control a brushless DC (BLDC) motor . See the relevant schematic below:

Everything is powered by a 6-series li-ion battery pack. The +15V net is directly connected to the 4th cell, the +BATT net (about 24V) is connected to the 6th. The nets PHASEA, PHASEB, and PHASEC are the three phases of the BLDC motor.

The inputs DRV_INHx, DRV_INLx, and DRV_MODE are driven directly by an MCU (not shown) with 3.3v gpio. The rest of the pins are connected as shown in the schematic.

The NMOS fets are BSC007N04LS6ATMA1 parts.

On my first board, I was able to get the circuit working to drive the BLDC motor for a few test runs, so I am convinced that this circuit at least somewhat works. However it did not run very long before things stopped working. The high side fets seemed fine, but I noticed that for all of the low side fets (Q4, Q5, Q6) the gate nets were shorted to ground. I removed the fets from the board and verified that the shorts were not internal to the mosfets; no short between gate and source. All of the gate nets were still shorted to ground on the board, however, leading me to believe that the shorts are internal to the driver ic.

On a second board, it seems a similar thing happened. This one failed a bit more quickly and spectacularly burning a small hole in the driver ic and releasing a puff of smoke. High side fets seem fine, but again the low side fets had their gate nets shorted to ground. I didn't remove the fets on the second board, but I assume its the same deal as with the first.

Any ideas on why this is happening? I am beginning to suspect that it is due to the 0 ohm gate resistors I have populated combined with the PWM I am using to drive the BLDC motor, possibly causing too much current source/sink for the driver IC. The datasheet call out 750mA source current and 1500mA sink current for the bootstrap gate drive architecture. I originally though this was limited by the part itself but I am beginning to wonder if this was called out so that the circuit designer would externally limit the current to these amounts.

Or it could be something entirely different that I am not seeing or have missed in the datasheet. Anyone have any experience with this part? Any thought?

Answer 1

Yes. That is not one of TI's so-called smart gate drivers. You absolutely MUST put resistors in series with the MOSFET gates, and the values can be pretty critical.

It is not surprising at all that you are blowing up gate drivers with zero ohm resistors. Here is what I think is going on.

The high side is turning on so fast that the low-side drain voltage (PHASEA-PHASEC) rises rapidly. The miller capacitance on the low-side MOSFETs transmits some of that voltage spike to the low-side gates. The driver tries to keep the low-side gates low, but to do so it has to absorb a lot of energy, dying in the process.

Please read the answer to this question: What is miller shoot through voltage (aka cross conduction)?

You may not actually be getting shoot-through because your MOSFETs are not being destroyed. But the low-side gate drivers are absorbing a lot of energy keeping the low-side FETs off. And it seems that energy is destroying them.

High side gate resistors will slow-down the turn-on of the high side MOSFETs and save the low-side drivers from getting blown up. Your goal is to have the Miller plateau to be at least 200 ns. Or you could say that the rise time of PHASEA through PHASEC should be at least 200 ns. At least to start. You can tune it once you have it under control.

Qgd for your MOSFET is 11 nC (from the datasheet). So the desired gate drive current is about 11 nC / 200 ns = 0.055 A. If the gate drive voltage is 15 V (which is kind of high, by the way) and the plateau voltage is 2.6 V (datasheet) then the target gate resistor, RG, should be :

RG = (15 - 2.6) / 0.055 = 220 Ohms

That seems kind of high compared with typical values. Maybe I made a mistake, or maybe you just have a low-capacitance transistor and a high gate drive voltage.

The low-side gates should have the same value resistors as the high-side. But the easiest way to observe the low-side turn-on time is probably to look at the Miller plateau in the gate. You want the Miller plateau during turn-on to be something like 200 ns.

If you don't know what I mean by "Miller plateau" read this post: Relationship between the gate-charge graph and the Vgs waveform

To avoid destroying any more drivers while you experiment, use a lower input voltage and just generally go easy. Use an oscilloscope to monitor how fast your FETs are switching and try to tune the gate resistors.