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I found many examples of IC internals for CMOS Hi-Z (tristate) buffers, but none for the TTL family.

I guess that in the TTL world, the "open collector" is much more common, but I see that there are some three-state 74xx also.

The following circuit would be my naive attempt to do a discrete Hi-Z buffer.

I know that the inputs and outputs are not TTL, but I wanted to know what happens if voltages are in-between. It even exhibits a nice analog switch property.

Is there a more standard way?

Hi-Z TTL Buffer

ocrdu
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Steve Schnepp
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  • Standard way is any way that results into inputs and outputs adhering to the standard. For example the TI 74125 datasheet contains internal schematic of a three state TTL buffer. – Justme Jul 12 '22 at 19:37

2 Answers2

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An open-collector buffer just has to leave out the top output transistor(s), but with three states, you have all the normal output transistors, and in addition have to ensure that all are disabled in the Hi-Z state.

The SN74LS125A datasheet also includes the schematic for the SN74125:

SN74125 schematic

To get the standard TTL input and output characteristics (without using PNP transistors), all this is necessary.

Other TTL devices with 3-state outputs have pretty much the same internals, but the datasheets no longer show the details.

CL.
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Consider the standard TTL output cell, then consider splitting the pull-up and pull-down sections. Add inverters and gates, and that's how you synthesize a tristate gate (e.g. 74126, datasheet includes equivalent circuit, well heck, there 'ya go!).

And that's easy enough, so you get tristatable buffers, or muxes/selectors, working in one direction, very often.

A transmission gate, can be done in bipolar, but it's much more difficult; the usual way is a complementary pair of current sources (source and sink), to push base current into, and pull emitter current out of, the transistor; when no base current is applied, it's open both ways (assuming applied voltage is less than Veb, which is fine for 5V logic levels), and when biased, C and E saturate together -- and the saturation is maintained even to reverse bias (inverted operation), albeit having reduced hFE(inv) in most types.

Indeed, because inverted Vce(sat) is extremely low (can be just a few mV), these were used in very early high-performance DACs -- before JFETs and MOSFETs replaced them, not to mention ICs over discrete solutions (yes, a DAC made of arrays of 2N3904s or whatever -- the '60s were rough days!)

Tim Williams
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