What prevents MOSFET drain-to-gate leakage current?

Question

What in the structure of a MOSFET prevents leakage current flowing from the drain to the gate of a MOSFET when the drain is at a higher potential than the gate? I am assuming that drain-to-gate leakage current doesn't exist at all because it seems to me that if it did it would be a central MOSFET datasheet parameter as this current from the drain could charge the gate and turn the MOSFET on. If however drain-to-gate leakage does occur as a very small current, what keeps it from ever being a consideration in circuit design or in component evaluation?

Answer 1

I'm answering the question of how a power MOSFET can let you have e.g. a 500V Vdg while Vgs is limited to 20V.

Power MOSFETs have an asymmetric vertical structure, like this:

The breakdown voltage is determined by the characteristics of the N region between the drain and gate. The maximum current is determined by the size of the channel. In a vertical MOSFET, these can be varied separately, so you can have both a high on current and a high breakdown voltage.

Answer 2

There are two familiar cases here:

1. The usual integrated circuit (IC) case, where lateral MOSFETs are formed, covered in gate metal/oxide, over the whole channel;
2. Power MOSFETs, which are made in more compact/highly optimized structures, offering much higher voltage ratings (silicon parts are available rated 2500V or more!).

The other answers have covered #1 more or less, I think, and this is perhaps the less interesting case: in ICs, Vgs and Vds are almost always only within V_DD to V_SS. It doesn't really make sense to think of leakage from a channel that's not higher in potential than the gate anyway.*

So I also suspect your question may be more angled towards #2. Note that IC-style MOSFETs are essentially unavailable as discrete components -- almost any MOSFET you see on a board, will be some type of power MOSFET.

And as for power MOSFETs -- There is a fairly obvious(?) disconnect, I think, between the usual cartoon of a MOSFET (gate lapped over the whole channel), and a power MOSFET that obviously is handling a whole hell of a lot more than the, whatever, 20V say that the gate oxide is rated to handle! So what are they doing?

Two things. Back in the bad old days, when MOSFETs were still new, lateral MOS was indeed still the technology of the day. To handle the higher voltages, gate metal simply wasn't deposited over much of the channel length; instead, a heavier oxide layer, and a "field plate", tied to drain, was placed there. This effectively biases that part of the channel on, but with much less gain (read: less electric field per volt -- again, thicker layer), and so voltage can distribute along the channel, well, if not better necessarily, then differently at least. (I'm not sure exactly what designs they did of this; it would also make sense to have a tapered oxide under the field plate, but I don't know that any stereolithography process has ever made a sloped oxide surface; that would be very difficult to fab the usual way, at the very least.)

I don't know enough about laterals, to say what kind of ratings they achieved; maybe a couple hundred volts?

Note that, meanwhile, the channel diffusion itself is deeper, lighter, less abrupt -- just as the case for a higher voltage diode or BJT.

I was about to explain modern vertical (VDMOS) here, but I see @AdamHaun has beat me to it! In that case, the voltage is dropped across the p- epi, and, I suppose the oxide at the bottom of the trench could be thicker, though I don't know that that's done..?

Anyway, the structure very much resembles any other high voltage device -- diode or BJT -- where there's a large drift region of lightly doped (sometimes intrinsic even, as for some rectifiers -- though I don't think transistors can use intrinsic, so, not quite that low doping) semiconductor, across which most of the voltage is dropped (depletion region), and then there's a tiny bit of hardware at the surface, shooting charges (electrons/holes) into that depletion region.

The figure (https://i.stack.imgur.com/c3pBM.png) I think is not to scale; the gate stuff is actually all very small, i.e. 100s nm wide, and perhaps a few times taller (not sure of the exact dimensions; and it does vary with process of course), while the drift region is several to 10s of µm tall. So this allows the electric field to drop mostly through the bulk, without building much additional E-field at the base of the gate trench, so that breakdown (avalanche), when it does occur, doesn't cause too much stress around the gate, which might lead to failure.

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*There is a different gate leakage mechanism, known as "hot carrier injection". I'm not real big on the details of this myself, but it has to do with operating a transistor very near its process limits (close to breakdown); the high electric field accelerates the carriers crossing the channel (i.e. raising to higher energy levels: hence "hot"), and these high energies being generally present in the area, allows some to tunnel or diffuse into nearby structures -- even through fairly high energy barriers, like SiO2 (an insulator, i.e. electrons don't move very far through it normally!). This phenomenon allows depositing charge into an otherwise fully unconnected piece of metal placed near/on the channel: thus a floating-gate EPROM cell can be formed. The deposited charge, of course, biases the gate, so that when normal gate voltages are applied to the second (wired) gate, the transistor may read as on or off, and thus a bit of information can be stored, persistently. This usually needs similarly drastic means to relieve the charge -- UV exposure for example (photoelectric effect) -- but electronic methods have also been developed, hence EEPROM and Flash. (I've not read up on these in a long while, actually, so I will hold off on attempting an explanation; others can chime in.)

The significance of this effect, can also be seen in MOSFETs: at high Vgs (above ratings), carrier injection can occur due to the few carriers that do leak across the barrier; if they get stuck, a permanent shift in Vgs(th) results. Of course, if too many get stuck in one place, a defect can form; or if too many flow in a local region, same idea, and gate rupture occurs. Vgs(max) is rated to avoid both effects.

Likewise, the hot-carrier (channel) effect can cause shift in Vgs(th), or eventual failure. While many MOSFETs are rated for avalanche robustness, take care that those ratings are indeed one-time -- typical parts only survive a few such hits before destruction. And repetitive avalanche can cause incremental wear, by trapping charges in the oxide. This is why I always recommend control of Vds: if it cannot be ensured in normal operation (e.g. with adequate supply bypass, design of the switching loop, etc.), then a clamp diode or TVS should be added to sink the excess, avoiding avalanche operation. (TVS diodes are made with careful control of trapping sites, so can withstand essentially unlimited avalanche.)

(Supposedly, some MOSFET types are more robust than others, in terms of repetitive avalanche. But I haven't seen a good argument for why this might be, or how to identify them. One explanation could be, avalanche is made to occur in the space between gate trenches, so the hot carriers are relatively distant from it; but I don't know what families, if any, have such a feature.)

Answer 3

The drain to gate (and source to gate) resistance comes about because of the 'O' in 'MOSFET'. This drawing (By Brews ohare - Own work, CC BY-SA 3.0) shows a schematic of the MOSFET structure.

The pale layer between the gate (G) and the channel (between the source and drain, S and D respectively) is insulating -- in a silicon device, it's silicon oxide, so it's basically glass or quartz. That layer is a good insulator.

This doesn't mean the insulation is perfect - any two electrical conductors will leak a little bit. In the case of most discrete MOSFETs, the leakage is utterly insignificant compared to the intended usage of the part. Most MOSFETs are intended as power devices, and gate drives need to have very low impedances to drive the gate quickly enough.

If someone were selling you a FET where the isolation between the gate and source or drain is a selling point, then they'd be sure to tell you -- and they'd have recommended board layouts for you because when you get to that point the board can potentially leak more than the part itself.

Answer 4

There is an insulating oxide layer between the gate and the source/drain structures. As long as you don't apply a high enough voltage to breakdown that oxide layer the leakage current flowing through it should be extremely small (nanoamperes, for example).