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I am new to AXI interface and need help understanding the flow of data from master to slave. I am trying to make a project using AXI4 with the following components using Nexys A7 board:

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I want to use the ADC to acquire data, and only save data that passes a certain threshold to the BRAM. I wanted to trigger the acquisition using JTAG. So the JTAG to AXI is the master while the rest of the IPs are slaves. I understand that the interconnect is the bridge that connects the IPs in the FPGA (does address offsets).

How can I implement such thing using AXI, I want the data to be triggered by JTAG and when the trigger is received by the XADC block, thresholded data is saved into the BRAM. I want to also read the data using JTAG. So how do I transfer data from slave to slave, is this something related to the interconnect?

I will be acquiring data in chunks and not continuous mode so that the BRAM is filled and overwritten in the second trigger.

Shannon
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    Use native interface of Block RAM instead of AXI. And design a AXI master based glue logic to read the data of interest from the slave, analyse, and write directly to BRAM. – Mitu Raj Jul 06 '22 at 18:04
  • So the BRAM would be part of the AXI master, and the master AXI has only the XADC as a slave? Is there a reason for changing the BRAM to have native or just simplicity? – Shannon Jul 07 '22 at 05:10
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    For simplicity, performance and minimal area. Especially since only one master needs to access the BRAM, no need of connecting it on the interconnect. – Mitu Raj Jul 07 '22 at 05:15

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