I dont understand what is DRAM Precharge.
Is DRAM precharge used for reading the memory, is it applied before reading the row? or is it used closing the row access?
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The role of the precharge in DRAM is to set the voltage of columns to Vdd/2. As they have significant capacitance, they can be considered as capacitors. So, to change their voltage, they must be charged by a powerful voltage source.
Then, the precharge source is removed and the weak memory cell is connected to the column. Depending on its state (0 or Vcc), it slightly "pulls" the column down or up (changes its voltage with a few hundred milivolts).
Finally, the powerful sense amplifier (regenerative circuit like a latch) is connected in parallel and it finishes the work - reads the memory content and refreshes the memory charge (voltage).
EDIT: An answer to @jayded-bee's comment
DRAM datasheets will tell you that the correct command sequence is activate -> read -> precharge; Precharging comes last.)
The command sequence is constantly repeated so we cannot tell which is first and which is last. Precharging is a preparation for the next read; that is why it is listed last in the datasheet. But for the purpose of understanding it is more appropriate to consider it as the first.
Circuit fantasist
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1@ Aakash, Have you seen these excellent movies about [DRAM](https://youtu.be/8zhr72a6tqQ) and [SRAM](https://youtu.be/KrqyvpU9Cu0)? Maybe they will give an answer to your question? – Circuit fantasist Jun 25 '22 at 19:37
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1@Circuitfantasist Indeed fantastic videos, but they don't answer the last question. In fact, they go as far as to say that a read operation must begin by precharging the bit line to Vdd/2. (DRAM datasheets will tell you that the correct command sequence is activate -> read -> precharge; Precharging comes last.) – jayded-bee Jan 08 '23 at 23:49
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@Circuitfantasist but your edit is misinformed. If you have direct access to a memory controller (e.g. in an FPGA), you can try this out: After initializing the memory chip (ZQ calibration and setting mode registers), you can activate and read from the memory immediately. The command pattern is clearly defined by the state machine diagram and the relevant timing parameters. It is at the very least misleading to say that "we cannot tell which is first and which is last". We can tell, because that's how JESD79 specifies it. – jayded-bee Jan 09 '23 at 13:39
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@jayded-bee, It's hard for me to imagine what's going on in your head, but it's a simple electrical circuit of two capacitors with very different capacitances and different voltages connected in parallel. That's all. – Circuit fantasist Jan 09 '23 at 14:29
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@Circuitfantasist That's not the question. We both know what a dynamic memory cell looks like and why a precharge is necessary. The question is simple: Why do we activate and read, but only THEN precharge the bit line (as specified by all the JESD79 variations)? – jayded-bee Jan 09 '23 at 14:47
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@Circuitfantasist This is the first use of the term "preloading" I've encountered w.r.t. DRAM. What do you mean by this? We've established already that the commonly taught procedure instructs us to precharge the data line, then we can read. OP and I are asking why actual chips will ask you to precharge as the LAST step of the read process ("why precharge command closes the row"). – jayded-bee Jan 09 '23 at 17:44
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1@jayded-bee, Sorry, it was my fault. It has to be: To read the bit line, we have first to precharge it to Vdd/2; so precharging precedes reading. In other words, we can read the bit line if we have precharged it. Regarding your last question, I think, as I have already said, that "actual chips will ask you to precharge as the LAST step of the read process" for the purpose of the next reading. – Circuit fantasist Jan 09 '23 at 18:58