Peak switching power in MOSFET as seen in LTSpice, and reduction using snubber or gate resistor

Question

I am exploring a tentative design to limit current for charging a VFD bus link capacitor from the AC mains. Simple analog current limiters using resistors and transistors are inefficient and problematic when dealing with peak charging current from a full wave bridge rectifier, as I discovered in answering a similar question recently. So I think this will require a switching regulator design using PWM and an inductor. I simulated a circuit using LTSpice that seems promising, but I see very high power spikes when the MOSFET is turned on and off.

This is to be expected, as the device will transition from a condition with as much as 350 V when OFF, to a peak current of up to 20 A in the inductor, so during switching there may be simultaneously as much as 7000 W. LTSpice shows spikes of several thousand watts, but duration is in the order of 100 ns.

I was able to somewhat reduce the amplitude of these transients by using an RC snubber across the device, and with a gate resistor which reduces the switching speed, but both methods dissipate power. I have also found a lot of variation among various NMOS models. When I calculate the average power over a half wave at 60 Hz, it is about 5 W, which is acceptable. But I am concerned about reliability issues due to the high switching transients. I have designed and built similar switching circuits, and they have worked OK, but I'd like some confirmation that these transients might be ignored.

Here is the circuit as it stands. A practical implementation would require a number of refinements, but this is to prove the general principle.

I found that the commutating diode D2 was exhibiting several hundred A of reverse conduction, which caused much of the excessive power spikes noticed. I replaced it with three 150 V Schottky devices and the circuit operation now seems reasonable. Here is the new simulation:

Answer 1

but I'd like some confirmation that these transients might be ignored.

Absolutely not.

They cannot be ignored but, you can easily check to see if the device you have chosen is suitable. Open the data sheet for the device (R6020PNJ) and navigate to the safe operating area graph: -

The red parts are by me and tell you that the maximum instantaneous power that can be handled by the device is 6 kW providing it lasts for no more than 100 μs.

during switching there may be simultaneously as much as 7000 watts

Find a more powerful device.

It's tempting to think that for your pulse duration (100 ns rather than 100 μs) you can just extend the SOA graph up in stages but it doesn't work like that. In my experience, devices that have the minimum time limit specified as 100 μs are usually weak for most jobs. Most good MOSFETs will have the 10 μs duration plotted and, the peak power will be significantly more than that at 100 μs duration (probably at least 3 times greater and sometimes up to 10 times greater) such as this SiC device from ON semi: -

Answer 2

Yes, this is a fine way to do it, given all the usual caveats of power electronics design, including accounting for stray inductance of the switching loop, peak and average power dissipation, thermal management, current control, and other protective features like mains surge or output faulting.

For example, I've designed and built some limiters myself, albeit for a lower power level -- 30V 20A:

These use two transistors anti-series, with a hysteretic current mode control, to implement bidirectional current limiting. Switching is done at around 200kHz, and is limited to a fault duration of 150ms, or until the clamp diodes overheat. An optional ground-return connection can be used to save power dissipation, allowing more fault cycles before the thermal limit kicks in. Finally, the optimized discrete circuit design draws minimal supply current, giving a lifetime of some months continuous operation on a 9V (PP3) battery. (This is rather unimpressive on the whole, actually, but I didn't see any ICs available to implement this function, so had to build it myself(!). Doing it from common ICs (logic, comparators, gate drivers) would give significantly shorter battery life. Go figure!)

A similar approach could be applied for commercial/industrial voltages and currents as in your application, given suitable design changes -- probably the discrete circuit wouldn't be so practical anymore, and an auxiliary supply would be available to power the controls. Bigger transistors would be required of course, especially with mains surge requirement in this location -- probably something like 1200V SiC MOSFETs, with a MOV at the input, would do. And with thermal protection, and a free ground return path (no clamp diodes required, as in my inline case), a compact design should be quite reasonable.

Incidentally, notice the inductor can be quite shite. Core loss is essentially irrelevant; even if it has a Q of 5 (typical for #26 powdered iron around 100kHz), it's only active for some hundreds of ms, and out of the several ~kW (DC) delivered, it dissipates, well, about 1/5th of that, but that's only a few paltry J of energy, out of a big chunk of iron/copper/ferrite -- it'll barely heat up.

The main reason you don't see these sorts of things, by the way: they're simply added cost. You need a BIG transistor to handle that much (steady state) power, plus precharge, plus surge. An NTC resistor, and optional bypass relay, is so much better value.