Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

Question

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which parameter value is wrong.

For the Quartus I have write checks on the initial block:

module test_module #(parameter TEST_PARAM = 1)
   (input some_in,
   output some_out);

   initial begin
      if(TEST_PARAM == 1) $error("TEST_PARAM must be zero");
   end  
   assign some_out = some_in;
endmodule

The Quartus displays my error correctly and stops synthesis.

When I try to synthesis on the Synplify, it did't display my error, synthesizes to the end of my code and set warning:

CG532: Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored

If I extract $error(...) from the initial block to the module body the Synplify behaviour is the same, but the warning is:

CG505: Ignoring system task $error. Supported only within an assertion When I try to use an assertion...

module test_module #(parameter TEST_PARAM = 1)
   (input some_in,
   output some_out);

   assert (TEST_PARAM == 1) $error("TEST_PARAM must be zero");
   else $error("good!!");

   assign some_out = some_in;
endmodule

...the Synplify synthesizes to the end of my code without any warnings or errors.

I have read on pg.15 Synplify Pro Language Support Reference Manual next sentences:

Ignored Verilog Language Constructs. When it encounters certain Verilog constructs, the tool ignores them and continues the synthesis run. The following constructs are ignored: <...> Calls to system tasks and system functions (they are only for simulation)

Is it means that a SystemVerilog code can't stop syntezis on the Synplify with custom error at all? No way?

Try $fatal instead of $error in your assertion. – Mitu Raj Jun 27 '22 at 12:39 — Mitu Raj, Jun 27 '22 at 12:39

Greg · Answer 1 · 2022-07-19T06:13:06.720

0

I don't know about Synplify specifically, but SystemVerilog does cover elaboration system tasks (see IEEE1800-2017 § 20.11). This feature been part of the LRM since IEEE1800-2009. So the follow should throw an elaboration error if TEST_PARAM is 1.

module test_module #(parameter TEST_PARAM = 1)
   (input some_in,
   output some_out);

   if(TEST_PARAM == 1) $error("TEST_PARAM must be zero"); // Inferred generate statement
 
   assign some_out = some_in;
endmodule

An alternate solution is to use a generate conditional statement to instantiate a non-existing module for your fail scenario. This will not print as helpful of a message as $error but better than nothing. I answered Is there a way of conditionally triggering a compile-time error in verilog? back in June 2013 with this strategy.

module test_module #(parameter TEST_PARAM = 1)
   (input some_in,
   output some_out);

   if(TEST_PARAM == 1) begin
     illegal_parameter TEST_PARAM_must_be_zero();
   end
 
   assign some_out = some_in;
endmodule

edited Jul 19 '22 at 06:13

answered Jul 03 '22 at 23:46

Greg

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The question was about Synplify. – Arseniy Jul 04 '22 at 14:18
1

Did you try the code? Synplify is a synthesis tool that can read Verilog, VHDL, and SystemVerilog files. Not every feature is the languages are supported. The OP code does the parameter check in an initial block which is evaluated at runtime in simulation, but systhesis tools usually skip initial blocks. My code does the check in the elaboration, many modern synthesis tools will run the check. I don’t have Synplify so I cannot test it, but I do know what it should support. For a precise answer, check with the vendor. – Greg Jul 04 '22 at 15:39
"systhesis tools usually skip initial blocks" Synthesis tools of Intel(Altera)/AMD(Xilinx) does't skip initial blocks exactly for supporting custom errors. The question was exactly about Synplify. "Did you try the code?" And you? Have you tried your own code with at least one synthesis tool before giving an answer? Or you just tried to write something remotely related to the question in the hope of getting a reward? – Arseniy Jul 18 '22 at 06:41
1

My answer works on EDA playground with Yosys 0.9.0 (an opensource synthesizer) https://www.edaplayground.com/x/N98K . Also used this strategy for parameter checking on various projects that reached mass production. I normally work on ASIC and those syntheiszers generally do not support initial blocks; FPGA follows similar but different requirements. I found a similar question I answered years ago, so I updated my answer with an alternative solution with reference link. – Greg Jul 19 '22 at 06:13

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

1 Answers1