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Is there any other advantage of a dual-gate MOSFET other than combining two single-gate MOSFETs in the common source + cascode configuration in a single package?

Does it have anything to do with reducing the inductance between drain1 and source2? Or maybe to reduce the capacitance from the source1/drain2 connection point?

nijoakim
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    Not the same if only because less capacitance when it matters most. https://www.electronics-notes.com/articles/electronic_components/fet-field-effect-transistor/dual-gate-mosfet.php Not sure you can do the mixer with discrete cascode. – DKNguyen Jun 02 '22 at 14:02
  • Temperature matching of two die. Though being in the same package, it'll be pretty good. – Aaron Jun 02 '22 at 14:04
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    [These answers might help](https://electronics.stackexchange.com/questions/69300/how-does-a-dual-gate-mosfet-reduce-miller-effect) – Andy aka Jun 02 '22 at 14:05
  • @DKNguyen: I don't see how that article answers that question. As far as I can tell, they never compare the dual-gate to two single-gate MOSFET, but only to one. – nijoakim Jun 02 '22 at 14:49
  • @Aaron: But why would you want the temperature to match in this configuration? The two transistors are in completely different configurations and I fail to see the point of matching. – nijoakim Jun 02 '22 at 14:49
  • @Andyaka: Yes, this speaks for that the capacitance in the connection point is smaller for a dual-gate. Will that give a reduction in bandwidth, though? Will the bandwidth not be dominated by the (larger) capacitance at the output of the cascode either way? – nijoakim Jun 02 '22 at 14:49
  • The capacitance being smaller is trivial. The AC signal voltage at the common point of the two MOSFETs is much lower than for a single MOSFET's drain hence, miller effect is dramatically reduced @nijoakim – Andy aka Jun 02 '22 at 14:52
  • Hmm I guess it never technically says what the difference is other than implying larger bandwidth. – DKNguyen Jun 02 '22 at 14:56
  • @DKNguyen and Andyaka: Yes, that is what the cascode configuration does, but that is compared to ONE single-gate MOSFET and not TWO. If you have two single-gate MOSFETs you also mitigate the bandwidth reduction because of the Miller effect, but the question is if somehow the performance becomes even better with a dual-gate MOSFET compared to TWO single-gate MOSFETs. – nijoakim Jun 02 '22 at 15:01
  • My link does not say why but does say that it is better. – DKNguyen Jun 02 '22 at 15:02
  • @DKNguyen: In that case we interpret your link differently. I would say it says it says that a dual-gate is better than one single-gate (not two, as state in my original question). – nijoakim Jun 02 '22 at 15:03
  • Isn't that what I said? I did just edit a typo though. You might have better luck finding why a pentode vacuum tube is better than tetrode. They seem to be more well known. There is probably a relationship there. – DKNguyen Jun 02 '22 at 15:04
  • Aha, maybe I just misunderstand. I assumed you answered the original question, which speaks about two single-gate MOSFETs. I did not realize you were talking about a single single-gate MOSFET. – nijoakim Jun 02 '22 at 15:07
  • You did not misunderstand. I misunderstood your previous reply. I am answering the original question. I interpreted your question as one dual gate MOSFET vs two MOSFETs in cascode. I interpret the article the same way. – DKNguyen Jun 02 '22 at 15:08
  • Let us [continue this discussion in chat](https://chat.stackexchange.com/rooms/136768/discussion-between-nijoakim-and-dknguyen). – nijoakim Jun 02 '22 at 15:10

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