I'm stuck on the print properties of uvm_tlm_analysis_fifo
handle with `uvm_info()
.
I made a simple sequence item as below.
class simple_sequence_item extends uvm_sequence_item;
rand bit[9:0] address;
rand bit[31:0] data;
rand bit wr_en;
bit acc;
function new(string name="simple_sequence_item");
super.new(name);
endfunction
`uvm_object_utils_begin(simple_sequence_item)
`uvm_field_int(address,UVM_ALL_ON)
`uvm_field_int(data,UVM_ALL_ON)
`uvm_field_int(wr_en,UVM_ALL_ON)
`uvm_field_int(acc,UVM_ALL_ON)
`uvm_object_utils_end
constraint c_sequence_item { data<'d40;
data>'d1;
}
constraint c_address{ address<'d500;
address>'d0;
}
constraint c_wr_en{
wr_en=='d1;
}
endclass
I have implemented with a declaration of simple_sequence_item
as the below,
class apb_scoreboard extends uvm_scoreboard;
simple_sequence_item seq_item;
`uvm_component_utils(simple_scoreboard)
uvm_tlm_analysis_fifo#(simple_sequence_item) fifo_exp;
...
virtual task run_phase( uvm_phase phase);
fifo_exp.get(seq_item);
`uvm_info(get_type_name(), $sformat("fifo_get seq_item from mon in Scoreboard : \n Address=%02h\n data=%02h\n wr_en=%02h\n acc=%02h\n", seq_item.address, seq_item.data, seq_item.wr_en, seq_item.acc, ), UVM_LOW)
endtask
But, the problem is that I got the System task was invoked like a function (it has no return value)
error message during compile.
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turnin
seq_item.address, seq_item.data, seq_item.wr_en, seq_item.acc ), UVM_LOW)
|
*E,NOTSYF (./apb_scoreboard.sv,46|105): System task was invoked like a function (it has no return value) [2.7.4(IEEE Std 1364-2001)].
How to print properties of uvm_tlm_analysis_fifo
handle with uvm_info()
?