UART oversampling

Question

I've read that for UART is over sampling used to recover some kind of “clock signal”. How is that exactly done and why is that needed? I already searched on the internet, but I didn't find any helpful information.

Some uarts will sample the input multiple times within a bit cell and have a voting scheme to determine if the data is a one or a zero. The uart is asynchronous and relies on the bit rate clock to be within a certain tolerance between the sender and receiver. If there is a difference, the error accumulates for each bit. For 8N1, there is 10bits, thus the last bit has accumulated 10 times the timing error. — Kartman, May 31 '22 at 08:35
Does this answer your question? [UART Receiver Sampling Rate](https://electronics.stackexchange.com/questions/207870/uart-receiver-sampling-rate) (or [perhaps this](https://electronics.stackexchange.com/questions/505515/how-bits-are-still-synchronized-in-asynchronous-transmission/505521#505521) or [maybe this](https://electronics.stackexchange.com/questions/371514/in-one-way-asynchronous-serial-communication-how-does-the-receiver-sync-up-its/371521#371521))? — Andy aka, May 31 '22 at 08:50

score 5 · Answer 1 · answered May 31 '22 at 08:45

Do not confuse clock recovery and UART oversampling, they are very different things.

Clock recovery is used typically in synchronous transmission and often uses a PLL to resyntesize the data clock from the edges in the stream (some kind of modulation like the Manchester one help with that).

UARTs on the other hand work differently: the clock to the UART block is a multiple (typically ×16) of the bit rate. Transmitting simple keep the bit time for 16 clock intervals.

On reception the signal is sampled at 16 times the bitrate and the edge of the start bit zeroes the bit counter. From then UART slightly differ in behaviuour and performance:

The simplest way is simply to sample at middle of the bit (at count 8); if the start bit isn't seen as 1 at the sample time that's a glitch and reception stops;
Some more evoluted UARTs do a triple sampling (typically at counts 6, 8 and 10) and a majority vote to allow some jitter;
The best ones keep detecting edges and zeroes the count on each transition to allow a frequency drift.

True oversampling is done only in the latter two cases, otherwise it's simply a way to keep the clock running, otherwise it should be stopped and started at each byte, which is difficult for various reasons. The original 50 baud teletypes were mechanically scanned and the start bit simply released a rotor cluch (the start bit actually started the mechanism!)

score 4 · Accepted Answer · answered May 31 '22 at 08:46

Two devices that communicate over UART are not synchronous, so device A uses its own clock to transmit, and device B uses its own clock to receive data.

The receiving device must check the incoming data pin at a larger rate than the bit rate, to determine when the transmitting device has began to send the start bit, so the receiver can sample each data bit right in the middle of the bit, with as much margin as possible from the transitions regions.

Typically the oversampling rate is 16x which generally allows the bit rate clocks to have 1% to 2% tolerance.

UART oversampling

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