How to finish the forever statement on run_phase in UVM?

Question

I'm trying to understand forever statement in raise_objection()/drop_objection(). I thought that the forever statement will be finished after drop_objection(). But, the below forever statement does not finish.

    forever begin
        q_trans_addr.push_back(trans.addr);
    end

So the simulation be hanged. It couldn't finish. What am I supposed to do to finish if I want to use forever statement in run_phase()?

class component_b extends uvm_component;
    transaction trans;
    int m_num_rx;
    logic [31:0] q_trans_addr[$];
    uvm_tlm_analysis_fifo#(transaction) m_analysis_fifo;
    `uvm_component_utils(component_b)
    
    function new(string name, uvm_component parent);
        super.new(name, parent);
        m_analysis_fifo = new("m_analysis_fifo",this);
    endfunction
    
    virtual task run_phase(uvm_phase phase);
        phase.raise_objection(this);
        repeat(m_num_rx) begin
            #300;
            `uvm_info(get_type_name(), $sformatf(" COMPB Before calling analysis fifo get method"), UVM_LOW)
            m_analysis_fifo.get(trans);
        end
        forever begin
            q_trans_addr.push_back(trans.addr);
        end
        phase.drop_objection(this);
    endtask
endclass

Your code does not make much sense so it is unclear what functionality you are looking for. The repeat loop would just overwrite each trans you are getting. Maybe you just need to move the `q_trans_addr.push_back(trans.addr);` as the last statement of the repeat loop, and remove the forever loop. You need to explain how it is supposed to operate before anyone could show you how to fix it. — dave_59, May 27 '22 at 16:51
@dave_59 That's why I used m_analysis_fifo.get(trans); to prevent overwrite when I am getting. I understand that uvm_tlm_analysis_fifo is working as FIFO, why does The repeat loop would just overwrite trans? How to avoid the overwrite from it? Could you please guide me ? — Carter, May 31 '22 at 06:11
What kind of component is this? a scoreboard? what is put()ing into the analysis fifo, a monitor? and how are the put()s timed? what does #300 represent? — dave_59, Jun 01 '22 at 01:50

toolic · Accepted Answer · 2022-05-27T13:19:39.720

The forever block will never end. This means that you will never exit the block and never execute the drop_objection statement. Therefore, your test hangs.

Objections are not typically used in components; they are typically used in tests (classes extended from uvm_test). Remove the objection statements from your run_phase code:

virtual task run_phase(uvm_phase phase);
    repeat(m_num_rx) begin
        #300;
        `uvm_info(get_type_name(), $sformatf(" COMPB Before calling analysis fifo get method"), UVM_LOW)
        m_analysis_fifo.get(trans);
    end
    forever begin
        q_trans_addr.push_back(trans.addr);
    end
endtask

However, that forever block is a zero-time infinite loop, which may still cause your simulation to hang. You would normally have some other statement in the block, like a wait or a delay.

How to finish the forever statement on run_phase in UVM?

1 Answers1