The circuit shown below (with actual measured values) simulates correctly in as much that it provides some gain.
When I have built the circuit connected it to a signal generator using a 1mVp-p zero dc 1KHz sine input it does not work or at least on the oscilloscope there is no output signal.
So I was wondering if it needed a bias after the 39.7p capacitor. But then would this not spoil the JFET high impedandance?
What is the minimum components necessary to be added to get this to work in reality rather than just in simulation?