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I am designing a 4-Layer 0.5mm thickness PCB.

The outline is rather small which introduces some problems with panelizing the PCB. As I am a novice regarding these topics I would like to ask for help.

My PCB house does not have any recommendations on this topic. In their opinion "it can work, but I should try it" - the burden of low-volume customers.

My requirements:

  1. The PCB must be a "break-away" style within the panel.
  2. There must be test signals routed on the inner two layers for production testing.
  3. Pogo-pins cannot be used on the PCB directly as there is no room for pads and I would like to avoid micro-probes (sub 0.5mm landing pads.)
  4. The IC packages/passives must not be harmed during manual and automated depanelization.
  5. The top and bottom edge (see image) must be routed.
  6. V-dcoring is not possible due to PCB-thickness.
  7. Neither buried nor blind vias are possible.
  8. The "mouse-bites" must not extend beyond the PCB-outline if possible.

My current design is attached below:

PCB Breakaway Tabs

The blue lines indicate the break-away lines. The yellow lines are the board outline and the encircled (red) vias are used for test-signals.

Bottom Components

Top Components

The white lines do indicate the component outlines (0.25mm to component edge)

My Concerns:

  1. I am absolutely concerned that the components/the solder joints on the center ICs (top and bottom) will be damaged during depanelization.
  2. I am concerned, that the test-signal vias (0.4mm diameter, 0.2mm drill) on TOP/BOT will get ripped off due to their proximity to the board-edge - they are used "for the mousebites" as it is necessary to route signals across the break-away tab on the inner layers.
  3. I am concerned that the components (especially the 0402s) will crack during depanelization due to their proximity and the rather "stiff" break-away tabs. Therefore I project a reduced yield.
  4. I think that the mousebite vias are not far enough on the inside of the PCB outline and therefore the PCB outline will be violated after depanelization.
  5. I fear the possibility that the inner layer test signals will be "pulled out" during depanelization. Therefore, the signals will be broken and unusable within the perimeter of the actual PCB.

My questions:

As I want to get the design "some-what right" before ordering test-panels I appreciate any help.

  1. Are there cost-effective options available to avoid the routing of test-signals without adding any board-space?
  2. Is the "pulling" out of inner layer traces a problem?
  3. Is the proximity of the ICs/passives to the mousebites a problem?
  4. If so, how to avoid it in such a space constraint application? (See 1.)
  5. How are these problems/applications handled by professionals? What kinds of solutions do they apply?

PUSH

ElectronicsStudent
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    I think you'll be able to answer most of your questions by manufacturing one test panel and trying out all the features you plan to introduce. Having said that though, you can mitigate all your concerns to start off by respecting ALL minimum clearance requirements set by the PCB manufacturer + adding some margin on top of that if your constraints permit it. So, if the manufacturer has an 0.5mm minimum copper to board edge recommendation then you'd want to use that, with some margin on top if you can afford it... my 2cents worth, if it helps ... – citizen May 19 '22 at 08:40
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    Normally mouse bites are unplated holes. You’re asking for trouble, IMHO. And if you’re using crude hand depanelizing I’d be more concerned about reliability than yield. But it costs little to try some test panels. – Spehro Pefhany May 19 '22 at 13:37
  • Thank you very much for your response @SpehroPefhany I am planing to use some sort of fixure for the breakaway - just doing the mind games righ now. Regarding the mouse bites: What, in your opinion, is the trouble i am asking for? – ElectronicsStudent May 19 '22 at 17:55
  • Thank you very much for your response @citizen Every comment and suggestion does help. Do you have experience with this "fine track" stuff? Could you recommend some ideas on "the common pitfalls for novices" like me? – ElectronicsStudent May 19 '22 at 17:56
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    Can you put the mouse bites (aka stamp holes) in locations where they aren’t close to the components/tracks you’re worried about? The stress caused when depanelising depends on the amount of material left around these holes, so you will want to trade that off against the stability of the panel. – Frog May 20 '22 at 19:33
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    Looks like you're using plated-through holes which are going to break in a very messy manner with your traces peeling up and such like. – Spehro Pefhany May 20 '22 at 19:36
  • @Frog Currently i am not worried about the panel stability. Due to production equipment the Panel is a X=1, Y=... array so ridgid clamping during SMT and other steps is not an issue. (Not visible on images). Do you think, that damage to the components/joints can occure with a .5mm PCB (4L) ? I know this hard to answer - a educated guess maybe? Thank you in advance – ElectronicsStudent May 20 '22 at 20:37
  • @SpehroPefhany I do interprete your answer with a strong focus on the outer layers. I do fully get this. Do you think there will be an issue with the inner Layers peeling out also? To clarify: My idea is to route DUT-tracs for production testing through the mousebites - therefore the plated vias to avoid Copper<-> Edge limit constraints. I am thinking: Maybe it is possible to remove the outer pads but process the via as complete throughhole - without extra cost for buried vias. What is you opinion on this? Thank you very much! – ElectronicsStudent May 20 '22 at 20:43
  • Inner layers has a much better chance, but consider using unplated holes and running traces between them. – Spehro Pefhany May 20 '22 at 20:48
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    @ElectronicsStudent I’ve made some panels that will barely support their own weight (one 0.5mm web of FR4 on each side), if you’re ok with that then the danger of damaging the boards during depanelisation will be minimised. My feeling is that anything beyond 0.5mm from the snap-offs should be safe – Frog May 21 '22 at 06:48
  • @Frog Thank you very much! – ElectronicsStudent May 22 '22 at 10:37

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