I am trying to build a clock divide chain on an iCE40 UPduino card and have run into a problem with nextpnr. I've minimized a working / non-working example. This code works:
// constraints file as follows:
// set_io -nowarn clkin 20 # board clock
// set_frequency clkin 12
// set_io -nowarn clkout 21 # clk out to scope
// set_frequency clkout 100.6
// Top module is "clks"
module clks(clk12mhz, c);
input clk12mhz;
output clkout;
clk12to100mhz myclkgen(clk12mhz, clkout);
endmodule
module clk12to100mhz(clkin, clkout);
input clkin;
output clkout;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b1000010), // DIVF = 66
.DIVQ(3'b011), // DIVQ = 3
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) uut (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clkin),
.PLLOUTCORE(clkout),
//.PLLOUTGLOBAL(clkout)
);
endmodule
But changing clkout to scopeclk in the top module gives this error: "ERROR: IO 'clkout' is unconstrained in PCF." Here is the failing code:
// constraints file as follows:
// set_io -nowarn clkin 20 # board clock
// set_frequency clkin 12
// set_io -nowarn scopeclk 21 # clk out to scope
// set_frequency clkout 100.6
// Top module is "clks"
module clks(clk12mhz, scopeclk);
input clk12mhz;
output scopeclk;
clk12to100mhz myclkgen(clk12mhz, scopeclk);
endmodule
module clk12to100mhz(clkin, clkout);
input clkin;
output clkout;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b1000010), // DIVF = 66
.DIVQ(3'b011), // DIVQ = 3
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) uut (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clkin),
.PLLOUTCORE(clkout),
//.PLLOUTGLOBAL(clkout)
);
endmodule
Can anyone see what I am doing wrong in the second version?
