STA timing closure for asynchronous FIFO

Question

However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.

Both read_clk and write_clk are having the same clock frequency.

Could anyone advise ?

Please see below the reports from Vivado tool:

Why a do you use phase shift? Why a fifo? – May 03 '22 at 19:06 — , May 03 '22 at 19:06

score 0 · Answer 1 · answered May 03 '22 at 19:05

0

Let's consider that your clock is a 100 MHz one. The period is 10 ns.

Read clock has a phase shift of 270 degrees which corresponds to 7.5 ns.

Write clock has a phase shift of 90 degrees which corresponds to 2.5 ns.

The time difference between your two clocks is 5 ns. It is 200 MHz.

So depending on the clock frequency and shift, the constraint can be stronger (200 MHz) in my example

answered May 03 '22 at 19:05

I had added some Vivado reports outputs in my original question. Someone told me to use `set_max_delay` , but I am not sure how and which path to use it on. Should I use `set_max_delay` between read_pointer and write_pointer ? – kevin May 04 '22 at 01:12
Are your two clocks coming from the same oscillator? If it is not the case, yes you should put a set max delay – May 05 '22 at 12:22

1 Answers1