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For the following circuit, I need to find the small-signal impedance looking into the collector of the transistor at terminal X, not taking the load resistance Z into account:

enter image description here

My attempt at a SSM is: enter image description here

Now, as I understand it, the small signal impedance looking into the collector is just another way of saying output impedance (please do correct me if I am wrong). So we essentially need to find the small signal output impedance from the SSM.

To do so, we need to short the input, and apply a test voltage at the output. However, I can't see just by inspection what the input and the output even are on this SSM. Is \$v_{be}\$ or \$v_b\$ the input? Is \$v_{ce}\$ or \$v_c\$ the output?

My intuitive guess would be the input is between the base and small signal ground, \$v_b\$, and the output is between the collector and small signal ground \$v_c\$. But I have no real logic to justify this.

And if that were the case, if we shorted the input, we would be connecting the base to ground. And hence, the parallel combination of R1 and R2 should disappear in the calculation of output impedance.

But, as it turns out, the expression for the small signal output impedance is: enter image description here

And it does include the parallel combination of R1 and R2 (denoted \$R_{12}\$ here).

So, I'm sort of at a loss here, and clarification on (1) firstly identifying the inputs and outputs of the circuit and (2) why \$R_{12}\$ appears in the expression for small signal output impedance, would be much appreciated.

VJ123
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  • If we want to find Rout we are looking from the load resistance perspective. In this case, we see two paths for the AC current to flow. The first path is through Z resistance and the And the second one through BJT's From colletor into BJT collector. So, to find resistance seen from the collector terminal into the BJT we need to use a small signal model. – G36 Apr 13 '22 at 12:29
  • So in this case the input (for our test voltage ) is at the collector. Look here https://electronics.stackexchange.com/questions/613568/output-resistance-bjt-regarding-early-effect#comment1618479_613568 – G36 Apr 13 '22 at 12:34
  • @G36 Regarding your first comment, I have used a small signal model (or at least attempted to). – VJ123 Apr 13 '22 at 13:09
  • As for the second question, it looks like Vin source is connected via R1. And this is why R1||R2 are included in SSM. https://electronics.stackexchange.com/questions/265046/calculation-of-output-impedance-of-ce-emitter-bias-configuration-unbypassed-wi/276764#276764 – G36 Apr 13 '22 at 13:28
  • Today I found time to check your equation for Rout. It looks like a mess but despite this it is correct. Personally prefer this version $$ r_{out} = \frac{1}{h_{oe}} \left(1 + \frac{R_E}{R_E+(h_{ie} + R_{12})}\beta\right)+R_E||(h_{ie} + R_{12})$$ – G36 Apr 14 '22 at 13:49
  • Could you please show me your working and also the SSM you used? Maybe in an answer to the question? – VJ123 Apr 14 '22 at 13:51
  • But I already did that. Haven't you seen this https://electronics.stackexchange.com/questions/265046/calculation-of-output-impedance-of-ce-emitter-bias-configuration-unbypassed-wi/276764#276764 or this https://electronics.stackexchange.com/questions/613568/output-resistance-bjt-regarding-early-effect#comment1618479_613568 Do you have any questions about it? – G36 Apr 14 '22 at 13:53

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