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I have I2S MEMS microphones (transmitters, stereo) in slave mode and a microcontroller in master mode.

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When the WS pin iw 0 (low) the data available on the SD pin is for the left channel (microphone 1.) When the WS pin is 1 (high) the data available on the SD pin is for the right channel (microphone 2.)

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Is the data on the left and right channels synchronized or is the right channel data delayed by a few microseconds?

Would the delay depend on the sample rate. For example, for 16kHz sample rate, the right channel data is always delayed by 62.5µS?

JRE
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CuriousByte
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1 Answers1

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The datasheet is not 100% clear on this, but based on the datasheet block diagram it would be a reasonable assumption that the samples are latched at the same WS edge, and the selection only defines when it is transmitted out.

Justme
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  • Meaning both (Left and Right channel's) samples are taken at the same time but available to read one after another? – CuriousByte Apr 11 '22 at 10:13
  • Is there any reference code for this? I am not sure how data is packed when using both left and right channel. – Grabt234 Jan 19 '23 at 20:27
  • @Grabt234 Reference code for what? There is no software as this is a how data is transferred on a bus question and diagram in the question does describe how data is packed when using two channels. If you have a new question, ask a new question. – Justme Jan 19 '23 at 20:45