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A few years ago, Axiom Design Automation (acquired by Mentor Graphics in 2013) had a tool called Assertion Studio. It was a high-quality wizard to create assertions (including SystemVerilog ones).

Are there similar alternatives provided by any of the three major EDA vendors (Siemens, Synopsys, Cadence)? What about open-source tools?

Ideally, the tool should have the following features

  • assertion visualizer
  • assertion interpreter
  • assertion explorer
  • assertion assessor
  • assertion engines
nanoeng
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1 Answers1

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Cadence has bucket of tools under the umbrella of JasperGold (JG) Apps.

You may want to refer to Formal Property Verifier (FPV)

They support assertion based VIP called ABVIP too.

Sourabh Tapas
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  • The tools you listed are quite generic and can easily be found in the other two vendors (e.g. [Siemens' Questa](https://eda.sw.siemens.com/en-US/ic/questa/formal-verification/) and [Synopsys VCS](https://www.synopsys.com/verification/simulation/vcs.html)). I'm looking for a specific solution with the features listed in the question described above. – nanoeng Apr 18 '22 at 18:20