If I invert an I2S data line, it inverts the audio, right?

Question

It seemed obvious to me, but then I read all these audio forums where they're talking about overflow, tones, etc. and I just want to make sure I'm not missing something.

If you take an I2S signal:

and run the serial data (SD) signal through a logic inverter IC (leaving the clocks unchanged), the audio will be flipped and have a tiny DC offset added to it, right? No other consequences? No wraparound distortion or anything?

I2S spec:

Serial data is transmitted in two’s complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths.

So for example, if my ADC is outputting 24-bits of audio on a 32-bit word clock, with the remaining bits 0, and the unused channel all zeros:

Then for instance:

• the negative number 0xffffcd00 inverts to 0x000032ff
• the positive number 0x00001600 inverts to 0xffffe9ff

If the data were 3-bit, the values on the left would just become the values on the right:

b2	b1	b0	2C	~b2	~b1	~b0	inv
1	0	0	−4	0	1	1	+3
1	0	1	−3	0	1	0	+2
1	1	0	−2	0	0	1	+1
1	1	1	−1	0	0	0	0
0	0	0	0	1	1	1	−1
0	0	1	+1	1	1	0	−2
0	1	0	+2	1	0	1	−3
0	1	1	+3	1	0	0	−4

So it's just an inversion with a small constant DC offset (which doesn't matter for audio), right?

And the unused right channel just becomes 0xffffffff which doesn't matter because 1. that is also just a small DC offset and 2. we're ignoring it anyway, right? (It doesn't bleed into the left channel's bits or anything.)

(Actually, now that I think of it, the better option would be to invert the stereo 24-bit per sample stream, instead of flipping each mono 32-bit per sample stream earlier in the chain. I'm pretty sure that doesn't make any difference and it works fine either way, though.)

Answer 1

The difference between 2's complement and 1's complement is that for 2's, a carry-in of 1 is added to the complement. Using 1's will result in a bias of -1 on the value. Otherwise, the phase of the signal is just flipped.

Example:

• 16 bit 2's digital 1 = 0x0001
• 1's of that = 0xfffe
• add carry-in of 1 to make 2's = 0xffff

So the data are off by -1 if you only use 1's.

As far as data justification (16 vs. 24 bits), it should not matter so long as sender and receiver agree on both wordlength and justification (and why wouldn't they - that's basic to the protocol.) The lower-order unused bits should be ignored. So if the unused bits are flipped by an inverter they will have no effect at the receiver.