BMS design question

Question

I recently came across this popular BMS design and I am trying to understand the circuit design

There are some great technical discussions around it, like on robojax or this non-English forum.

Most parts are pretty straight forward. Below is my understanding of the the original schematics:

1. Balancing module: discharging through 100R RES when cell reaches certain voltage.
2. Battery cell
3. Protection module: pull down pin 1 when cell is over-voltage, pin 3 when under-voltage. This, through various transistors, would then control the MOSFETs
4. MOSFETs for over-voltage / over-charge protection
5. MOSFETs for under-voltage / over-discharge protection

My main question is what is the function of (6)?

This author mentioned that, during short-circuit event, (6) turns off MOSFET until after the load is removed. After load removal, the circuit would work normally again. robojax also did a great video experiment showing this function. However, my simulation on circuit lab shows that it would always pull down the MOSFETs gate and never allow the battery to discharge.

Could someone please explain?

Thank you

Answer 1

My main question is what is the function of (6)?

Subcircuit 6 prevents voltage across the main FET module-4 from rising to more than 1.2V. This voltage is dropped across the combined Rdsons of the FETs in the module. It is possible that base and wiring capacitance at the base of Q8 cause Q8 to delay turn on briefly and then to remain on when FET current drops but, if so, this is not a formal part of circuit function.

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Q8 is usually held off by the 1M across Q8_be.
When the voltage across FET_Module_4_DS exceeds 1.2V then the 2 x 1M resistors provide 0.6V to Q8, turning it on and clamping FET_module_4 gate to source.
This does not turn the FET hard off as the reduced FET gate drive reduces FET_DS drop and starts to turn off the clamping circuit - so the module remains on with a drop of about 1.2 V across it. There MAY be some hysteresis that I have missed, but if so I have missed it :-) .

This would be a very unhealthy state for the FET module to remain in for any period as dissipation is I_load^2 x 1.2 V.
Without following the whole operation I assume the path through Q7 may have a secondary controlling effect. Maybe not.

It is not obvious why the arrangement should always pull down the MOSFET gate as Q8 can only be turned on when FET Vds is >= 1.2v.