Weak edges over SPI data lines

Question

I am developing a driver for an SPI temperature sensor, and having some trouble with poor quality edges near the end of packet on the data lines.

While I am not experiencing any data loss, I am worried this is evidence of a larger issue; any suggestions on potential simple causes of this problem would be welcome.

Temperature Sensor Data Sheet

https://datasheets.maximintegrated.com/en/ds/DS1722.pdf

I would guess that nothing is driving the line during that time period, so the line voltage is only controlled by stray capacitance and input leakage. — user253751, Mar 24 '22 at 09:51
What are the four traces shown? I guess the top two are MOSI/MISO, and one or both of the bottom traces are a chip select? Please add more detail. Please also link the temperature sensor datasheet. — TypeIA, Mar 24 '22 at 09:52
@TypeIA They are the same traces, MOSI and MISO one is digital render other is the analog signal, top is MISO bottom 2 are MOSI — stmfunk, Mar 24 '22 at 10:02
You should also have a look at CS (or CS# as appropriate). I think you'll find CS is released at the point where the MOSI/MISO levels start to drift. The levels of MOSI/MISO are not defined when no CS is active and it's normal for them to go high-Z (at which point they are floating, and levels can drift as you see here due to gradual discharge of stray capacitance). — TypeIA, Mar 24 '22 at 10:05
If something else is not reading this correctly, try adding a 1k-10k pull-up on these lines. — rdtsc, Mar 24 '22 at 12:01
@rdtsc Unfortunatly it's a mass ordered PCB, I'll have to get the electrical engineers to do a respin of the board if it becomes a major issue — stmfunk, Mar 25 '22 at 08:25
@TypeIA I think it may be when the clock cycle ends as opposed to when the CS goes low, but it does seem like it's this — stmfunk, Mar 25 '22 at 08:26
@stmfunk Yep, I think Klas-Kenny's answer and comment are correct, especially that this is normal and nothing to worry about. — TypeIA, Mar 25 '22 at 08:27

Klas-Kenny · Accepted Answer · 2022-03-24T10:20:24.527

6

As you can see in this table from the datasheet, as soon as the Chip Enable signal goes low, the output of the slave goes into High-Z state until a read operation is initiated.

Then the output is essentially floating, so the voltage on the line is then determined by some pull up/down if present, or simply by any leakage current on the in/output.

Either way, the voltage on the MISO/MOSI lines really does not matter between the packages sent. So this behavior is both expected, and not an issue.

edited Mar 24 '22 at 10:20

answered Mar 24 '22 at 10:10

Klas-Kenny

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I had looked at extended the length of the chip select and that didn't seem to fix the issue. Is it possible the input goes High Z after the end of a clock sequence? I understand it is not an issue, I'd just like to know for future reference – stmfunk Mar 24 '22 at 10:43
1

@stmfunk Yes, it is very likely that the output goes High Z as soon as it has no more data to output, i.e. right after the last bit of a read sequence has been clocked out. – Klas-Kenny Mar 24 '22 at 10:45

score 2 · Answer 2 · answered Mar 29 '22 at 01:06

You need pull-up resistors. It's a bad idea to drive CMOS inputs with a floating voltage. The resistors can be relatively large, e.g. 50-500kOhm, so as not to waste power. The signals will then look reasonable. Remember that a scope probe is 10MOhm, so with a 500k pull-up, you'll see voltage 5% smaller than it is without the probe load!

Weak edges over SPI data lines

2 Answers2