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PCB tracks carry electric signals and these produce magnetic and electrical fields around them. Due to these fields, the PCB tracks have inductive and capacative cross talk with nearby PCB tracks.

I sometimes see design where signal tracks are crossing others on an immediately higher or lower layer. In my understanding, if a ground plan is not sandwiched between the two tracks, when a signal travels on one track, it will induce a signal on the other track due to cross talk.

When is it acceptable to have signal tracks crossing each other in the way I have described?

Voltage Spike
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quantum231
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    2-layer PCBs have plenty of signal tracks crossing without an intervening ground plane. What frequencies are you interested in? Does your application either have extremely high impedances (e.g. electrostatics/electrochemistry/etc), high dynamic ranges between weak and strong signals, or particular stringent noise requirements? – nanofarad Mar 22 '22 at 20:29
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    Technically the answer is "when the difference is not enough to matter for what you're doing" unsatisfying though it may be. Mainly high-rise time digital will interfere with precision analog because one produces the most noise while the other is the most sensitive to noise. – DKNguyen Mar 22 '22 at 20:30
  • See what I know is that, for high speed designs like involving DDR3 RAMs, we need to take extra care. In this case, we would not want that the PCB tracks cross each other. Therefore, in my understanding the above scenario is not acceptable. When is it acceptable, that I do not know and that is why I ask this question. I am trying to learn about PCB design. – quantum231 Mar 22 '22 at 20:32
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    DDR signals are not "conventional" signals so that is not surprising. They're very fast so often need to be treated as transmission lines, very high bandwidth so can produce a lot of noise, and also sensitive to noise than your typical digital signal because they are so fast. – DKNguyen Mar 22 '22 at 20:34
  • How do you describe conventional signals? – quantum231 Mar 22 '22 at 20:34
  • Just slowish digital I guess. Where you don't really need to worry about matching trace lengths, or having terminations, or transmission lines. Signals that you don't typically need to take other precautions with. And analog that doesn't need to be very precise. The analog is usually much lower bandwidth so won't produce a lot of noise but because it is analog it will be more vulnerable to noise than a digital signal. – DKNguyen Mar 22 '22 at 20:35
  • Alright fair enough, then there is one more thing. Nowadays there will be ICs that will have a fast edge rise (short rise/fall time) although the signal itself does not have a very high frequency. In this case these signals will suffer from things like reflection, ringing e.t.c. Have you faced such hardware so far? – quantum231 Mar 23 '22 at 11:44
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    When I say high frequency that is a misnomer. I really mean high bandwidth/fast edges. But infrequent fast edges aren't often considered to be very critical because you have lots of time to settle and they aren't generating noise often. Things like RS485 are slow but expected to operate over long distances so terminations are present there but I would not consider these critical either. – DKNguyen Mar 24 '22 at 13:49

4 Answers4

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Our standard stackup for multilayer (12, 14 or greater layer count) boards usually have two routing layers adjacent to each other, with a ground or power plane on either side of them. This organization is repeated throughout the stackup.

One layer of those pairs is primarily for routing signals in the X direction, and the other layer for routing signals in the Y (orthogonal to the X layer) direction. With this approach signal crossings are at right angles with very little (though not zero) coupling between them.

When signals on adjacent, or even on the same layer, run parallel, we have design rules that govern how long that amount of parallelism can be. Those rules include the type of signal (clock, reset, pullups, etc) and the edge rates involved.

How are the design rules established

It's a multi-step process, and to some extent depends on the capability of your tool set.

One of the first things we do is to establish the signal, or net classes that we need to accommodate the design. For example class 1 signals are the most critical and include clocks. For class 1 signals, we'll specify the two orthogonal routing layers that those signals should be routed on (say layers 6 & 7), spacing (say 30 mils) away from other signals, desired impedance (50 ohms +/- 10%), etc.

Class 5 signals might be power nets that don't require a full plane.

Class 7 signals may be signal return (GND) planes that require a full layer or multiple layers.

Added some more info about signal classes

There is nothing magical or sacred about the names used for the signal classes. They could be numbers as in the example I used above, letters (class A, class B, etc) colors (class red, class blue) etc.

Once the signal classes are defined, we assign each signal in the schematic to a signal class, using an attribute on the signal. For example, the name of the signal is an attribute. So is the signal class.

Then when we go to the layout and routing stage, the tool takes those attributes and uses them to assist in the routing. The drafting, or routing instructions tell the layout person the order in which to route the various signal classes. Those instructions may say "route all class 1 signals first", followed by class 4 signals, class 2 signals, etc. The signal classes are not necessarily routed in the order in which they are listed, which is somewhat arbitrary. Note that there is still a large amount of manual input in the routing and layout phase of the board. That is, it is not a fully automated, hands-off process,

SteveSh
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  • Interesting, how are the design rules for something so complex specified in the tool? At the end of the day it is only the tool which can run a design rule check to see if anything was violated or not. – quantum231 Mar 22 '22 at 22:58
  • Answer was to long to include as a comment, so I added it to the main answer. – SteveSh Mar 23 '22 at 01:32
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When is it acceptable to have signal tracks crossing each other in the way I have described?

Signal tracks are just pieces of metal, when you have two bits of metal with distance between them they function as capacitors. When you bring them closer together or have more area between them, it creates more capacitance. If creating more capacitance between different signal traces is acceptable then do it. High frequency signals/currents will pass through this capacitance, a designer designing for low noise or high frequency might not want to create cross capacitance between two signals.

Voltage Spike
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    Capacity is proportinal to area, so better cross it than let it run in paralell (of course best to keep a distance). 2nd best have it on different sides of the ground plane. – lalala Mar 23 '22 at 15:08
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It is almost always OK to have the signals cross on adjacent layers. If signals run close and parallel to each other on adjacent layers it is more likely that there will be cross-talk. Also, the layer separation is important. Normally the stackup will be designed so every signal layer is close to a plane layer. The signal will couple most strongly to that plane layer.

The adjacent signal layers should be far apart compared to the distance to the plane, if possible. On very high layer count boards, the layer spacing may not allow wide separation.

user57037
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It all depends on speed and the signal integrity requirements. One of the reasons it is recommended to have plane layers on either side of your tracks is to provide an uninterrupted return path under/above the track.

If your signals are fast (high frequency) enough and you have other traces running below and/or above them, you are breaking this return path. This can have severe implications for EMI and signal integrity.

I'm not sure what the conventional "crossover" frequency is where this starts to matter. For very low speed signals, like I2C for example, which operates in the kHz or low MHz, I doubt it matters. But for hundreds of MHz and up (for DDR memory for example or gigabit ethernet as examples) it is highly recommend that the traces have unbroken reference planes.

I'm sure this is only part of the story, but I hope that helps...

EDIT: mkeith makes a good point about the stackup being a large part of this. The layers being "adjacent" does not matter as much as how close the adjacent plane or signal layers are.

mooshoomatt
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  • ok, I understand your point about signal integrity, but why is it bad for EMI? EMI as in radiated emissions? – quantum231 Mar 22 '22 at 20:34
  • @quantum231 Yes. When you break your return path, the return current must take some other path (via the ground plane, vias, etc) to get back to the source. This increases the signal loop area/cross section significantly which increases radiated emissions and can easily couple into other circuits. – mooshoomatt Mar 22 '22 at 20:37