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Imagine a 12-bit DAC with a range 0.2V to 3.4V and its DNL spec given as ±2 LSB.

I want to increase this DAC in stair step fashion(as shown in below illustration) from 0.2V to around 3.2V with around 3mV step increases in total number of 1024 steps.

enter image description here

In this case, my theoretical step increase is 3V/1024 = 2.9mV.

For DNL ±2 LSB corresponds to 2 × 3.2V / 4095 = 1.5mV.

I'm trying to make sense of these two above. I'm aiming 1024 times with 2.9mV step increase and the DNL error is 1.5mV. Is there any way to tell how many times such error will appear for a whole 1024 step increase? What can we say about accuracy of such a situation?

GNZ
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  • You are mixing 10 and 12 bit specs above. It is 3/(2^12)= 1LSB for 12 bit, and DNL+/-.5LSB which is ~1.5mv. Without having raw data, it would be hard to say for sure. Assuming the error distribution is gaussian, you could estimate something like only 1% of errors hit that level. – pat Mar 17 '22 at 18:18
  • For 12-bit DNL in my case is given ±2 LSB. Which means 1.5mV. I wrote the same value in comments. Here is the datasheet https://www.st.com/resource/en/datasheet/dm00037051.pdf. And can you also give an estimate for atypical deviation? – GNZ Mar 17 '22 at 18:28
  • 12 bit is not 3/1024 step size (it is 3/4096). But yes it will be +/-2LSB for 12 bit. You only need 10 bit which is +/-.5LSB. Either way, you will get the 1.5mv max DNL. If you assume the errors are random matching errors that are gaussian distributed, you can calculate 3 std or worst case of +/-2LSB occurs about 1% or less of the time. Typical would be the mean or near 0 DNL. 1std is 70% of time around .5mv DNL ballpark. – pat Mar 17 '22 at 18:45
  • This paper has a more visual set of graphs showing histogram and DNL profile for a 10 bit DAC (Fig 7,8) in order to understand my comment better. https://www.researchgate.net/publication/224113046_A_10-bit_low-power_small-area_high-swing_CMOS_DAC – pat Mar 17 '22 at 18:53

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The theoretical step size is not change by the DNL. In your case for a 12-bit DAC with a 3.2V reference voltage \$V_{LSB}=\frac{V_{REF}}{2^N} = 0.781\,mV\$.

Keep in mind that this is the resolution of the DAC, not its accuracy. The information you provide does not tell us anything about accuracy...nonlinearity and resolution are separate, orthogonal characteristics.

Elliot Alderson
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  • What I'm interested is the error of step sizes(which theoretically would be zero if DNL were zero). DNL in my case is given ±2 LSB. Which means 1.5mV. And resolution is 3.2V/4095 = 2.9mV. Does that mean one minimum step increase x will be uncertain 1.4mV < x < 4.4mV. If so, this is a huge deviation and uncertainty. But maybe this DNL is the worst case which can happen few times that I don't know. – GNZ Mar 17 '22 at 15:02
  • I'm going to rotate a galvo-mirror with this DAC and I need even increments. So the deviation between step sizes is important. Im worried if deviation occurs a lot. – GNZ Mar 17 '22 at 15:05
  • @GNZ DNL alone won't tell you that. It is indeed the worst expected over the entire range and typically is much less than that. INL will give you an idea of how bad it really is, since the INL for any given output level is sort of like the sum of all DNL errors leading up to it. – evildemonic Mar 17 '22 at 15:18
  • @evildemonic Thanks a lot for this input. Now I found that in my case(12-bit DAC with range 0.2V-3-4V) INL is given as ±4LSB. So how can I estimate the roughly average deviation for minimum step increase? Is 4LSB the total error sum of 4095 steps? Can we then say the average deviation per step is 3mV/4096 = 0.7μV ? I appreciate your comment on this. – GNZ Mar 17 '22 at 17:17
  • @GNZ Yes, you could say that is the average deviation, but you want to look at the gain error too to see if the INL is more from that or the DNL. The problem with looking at the average is you just don't know how often that average represents reality. You can have positive or negative DNL for each and every step and you really can't know. Nothing beats getting the device (or several) and profiling them yourself. – evildemonic Mar 17 '22 at 17:20
  • But if there is DNL error at each step INL would be huge isnt it? DNL is 1.5mV. So isnt it unlikely each step there will be such large deviation? Is INL the sum of all errors? – GNZ Mar 17 '22 at 17:23
  • Keep in mind the DNL can be positive OR negative at each division, so could be really bad but sum to near zero making the INL look good. Yes, the INL is the sum of all errors. – evildemonic Mar 17 '22 at 17:24
  • Oh I see but thats really hard to measure. Strange that they dont present such info. Here is the DAC in my case part of a microcontroller. https://www.st.com/resource/en/datasheet/dm00037051.pdf I need to tell someone roughly an estimate about this. Its not very easy to measure down to that level each step – GNZ Mar 17 '22 at 17:26
  • This is one of the inherent difficulties when working with DACs. INL is calculated differently between manufacturers, but you can always think of it as the total deviation from the ideal transfer function across the entire range. DNL is just the worst case deviation step to step. Unfortunately that is about the best you can do from datasheets. If you need better accuracy I would recommend an external DAC as they can be more accurate and be better specified. – evildemonic Mar 17 '22 at 17:31
  • Less than 0.5 LSB DNL is not hard to find. The ones included "for free" in microcontrollers...well...you get what you pay for heh. – evildemonic Mar 17 '22 at 17:35
  • @evildemonic I want to find one with SPI. But scared if I can understand the DAC's SPI communication. They look a bit complicated to program. – GNZ Mar 17 '22 at 17:37