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An RGMII interface transmitting data at 1Gbps runs with a clock rate of 125MHz, and data is clocked out on both edges. Given that, it would appear that any skew between signals needs to be limited to less than 4ns max (and possibly less depending on the specific chips involved).

Let's assume that I am using a pair of 6-channel digital isolators. The propagation delay is constant and in the range of 10ns~20ns. Let's assume that within each chip the propagation delays are matched to within ±1ns. But between two different copies of the isolator chip, the propagation delay is not necessarily matched (one could be 10ns±1ns, the other could be 20ns±1ns)

If all of the transmit signals (TXC, TD0, TD1, TD2, TD3, TX_CTL) are on one chip (so their delay is matched to within ±1ns). All the receive signals (RD0, RD1, RD2, RD3, RX_CTL, RXC) are on the other chip (so their delay is matched to within ±1ns). The delay between the RX signals and the TX signals is not matched in any way.

Will RGMII work with a constant well-matched delay on all signals?

user4574
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  • Which digital isolator? Does it have a make, model and datasheet you can link to? – Justme Mar 14 '22 at 21:19
  • Why isolate the PHY from the MAC when the Ethernet side has magnetics? – Simon Richter Mar 14 '22 at 22:31
  • @Justme I don't have a model for a digital isolator. The fastest single ended isolators I am aware of only go to 150Mbps. I just need to establish that this approach can work in theory, then I will go through the trouble of finding an actual part. – user4574 Mar 15 '22 at 00:22
  • @SimonRichter I am making a circuit card that will have an Ethernet switch chip that is connected to several processors via RGMII. Each processor and the hub chip have their own independent power supply. My case is atypical in that I want a fault on one processor, its power supply, or any trace connected to it, to be isolated from the other processors and the switch IC. This includes faults where signals leaving the box short to high voltages, or a power supply goes out of regulation. The alternative to isolating at RGMII is several more sets of PHYs and magnetics. – user4574 Mar 15 '22 at 00:38
  • If you know a 125 Mbps isolator what is the part number? But it does not matter, gigabit RGMII data is four lines at 250 Mbps so it would not work anyway. – Justme Mar 15 '22 at 00:46
  • @Justme ADUM260, ADUM160, SI8660 are examples of 6 channel 150Mbps isolators. The MAX22166 goes to 200Mbps. Analog devices does make various LVDS isolators that go beyond 150Mbps. ADN4654 (4 chan, 2.5Gbps), ADN4654 (2 chan, 1.25Gbps), ADN4650 (2 chan, 600Mbps). But since they are LVDS I would have to use single ended to LVDS converters on both ends, and since they are less than 6 channels I would have to deal with chip to chip mismatch. – user4574 Mar 15 '22 at 02:14

1 Answers1

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There are really two cases to think about propagation delay. For both cases, you'll need

  • a. the setup/hold times provided by the chip producing the signals,

  • b. the setup/hold times required by the chip reading the signals

  1. For signals flowing in the same direction as the clock that controls them, you need

    • c. the maximum skew (delay mismatch) between signals and clock

    If the launch setup/hold, adjusted by the skew, still meets the setup/hold requirement at the destination, you're good. Matched delays help a lot here.

  2. If you have signals moving against the clock (or other control signals), such as with SPI (MISO flows opposite to SCLK) or DRAM interfaces when reading from the RAM, then you need both

    • c. total delay in the clock

    • d. total delay on the data signals

    And these add together -- matching doesn't help.

For RGMII, the clock flows along with the data signals in each of the two separate groups, so matching will tend to make everything work. But you still should calculate the setup/hold windows post-skew and compare to the requirement at the destination. Make sure to account for trace length matching as well as delay inside the isolator.

The exception is for MDC and MDIO, which have both kinds of flow.... the delay from isolators will limit the maximum clock rate for this sub-interface (but it is independent of the Ethernet link speed).

Ben Voigt
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