"what is the meaning of this statement in VHDL" You show three statements but I imagine you mean the third one, the assignment statement:
aIn : in STD_LOGIC;
signal oSyncStages : std_logic_vector(STAGES-1 downto 0);
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
In a clocked process, the assignment will implement a shift register.
For a vector type like std_logic_vector, attribute high
returns the highest bit number.
So if std_logic_vector oSyncStages
was an 8-bit vector numbered (7 downto 0) then this is actually:
oSyncStages <= oSyncStages( 6 downto 0) & aIn;
Using attributes to discover the characteristics of signals and types allows flexible designs to be written that work with, for instance, different widths of signals.
That is shown here, as oSyncStages
itself has its width specified by STAGES
. You don't show the source of STAGES
but it must be from a constant or generic.
All of this explanation can be found in VHDL reference information on the internet, and in more detail. That will cover basics, such as 'what are vector types'. Research further for yourself rather than asking low-level questions here, there's mountains out there already written that will help you learn and faster.