Should I place vias for each parallel decoupling capacitor?

Question

First of all, excuse my potentially poor understanding of electricity, I'm a low level programmer and I'm doing my first PCB (4 layer-stackup - signal/gnd/power/signal).

I was placing these two decoupling capacitors in parallel next to my microcontroller's power and ground pins (the bigger one is 1 µF, the other one is 0.1 µF) and I wondered :

Is it better to have only two vias as shown on the first image, so that current "must" flow through both capacitors before reaching the pin (and that's where I might misunderstand how current flows, maybe I have an understanding of it that is too "directional"), or should I also add two vias next to the 0.1 µF capacitor (second image) which I believe could reduce the parasitic inductance but makes me think that some current not filtered by the 1µF cap comes directly from the power plane through the 0.1µF cap to the pin ?

Answer 1

the first image, so that current "must" flow through both capacitors before reaching the pin

The (low-frequency) current flowing past the capacitors is irrelevant. What's important is how, when the chip needs to increase or decrease its current draw in a hurry, can that incremental current get to the chip.

These incremental high-frequency currents will flow in loops, from the ground pin, through the capacitor network, to the power pin. The vias to the underlying ground and power planes don't affect the current provided by the capacitors, they just provide a parallel path for the current, which will be most effective at low frequencies and diminishingly effective at high frequencies.

So more vias to power and ground are good, because they reduce the inductance of the current path that involves the planes. And placing the vias nearer to the chip is good, because again it reduces the inductance of that path.

But it is really a separate question from how the capacitors should be placed, until you want to get to the level of analysis where you consider that two current paths in parallel (one inductive and one capacitive) can produce an anti-resonance with very high impedance at certain frequencies. But avoiding that doesn't require anything new: just reducing the impedances of all the possible paths for current to complete the circuit from the chip's ground pins to its power pins.