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I am trying to mitigate a self turn-on behaviour in an inverter simulation. It is a 400V design using. The H bridge uses SPP20N60C3 MOSFETS. The AC frequency has been sped up to 500Hz instead of 50Hz (the problem is the same at 50 Hz) to speed up the appearance of the problem. The gate driver is an IR2110. I can provide the asc file if needed, and Infineon provides the SPICE model for the IR2110. NB: SPICE must used modified trap and solver set to alternate for the simulation to work. I used a spwm signal with a dead time control circuit using a duty cycle shortener circuit provided in this post : duty cycle shortener

The simulation shows a short current spike across all MOSFETS since they are all shorted, that happens when the complementary MOSFETS turn on. The spurious spikes on G1 and G3 gate signals are easily seen. I wonder if it is a simulation artefact, or if this would happen in real life. I tried to change gate resistance, having a 10K gate to source resistor, as most chinese driver boards application schematics include them (although IR2110 has active low drivers, so it should not be required ?)

Also, getting rid of the output LC filter does not change anything.

Any help appreciated. full schematic spwm control driver and H-bridge drain currents and gate signals

rodv92
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  • For now I am investigating the common mitigation strategies : adding a RC snubber across drain and source, and adding a small cap across gate to source to increase the MOSFET capacitance ratio and will post the efficiency improvement results – rodv92 Feb 10 '22 at 13:01
  • Your schematic is very difficult to read. It would help not only yourself if you added labels, changed the default colour scheme to have the labels red (or anything that stands out), and try to draw the wires to be easier to decipher. Otherwise, at a glance, having capacitors across pure voltage source (without `Rser` or some other series resistance) are completely uselss (unless you need the current through the caps, which is not the case), and it looks like normal capacitive discharge. – a concerned citizen Feb 10 '22 at 16:21
  • Thanks for your comment, I am currently redoing the schematic to make it more readable. As for the Vin input and the 0.1uF caps, it would be in practice the output from a rectifier bridge + PFC boost converter. I don't plan to integrate this stage into the simulation for now due to simulation time constraints. So for now I decided to not de-idealize the source. – rodv92 Feb 11 '22 at 09:40
  • It seems that adding a 1nF cap across all mosfets from gate to source helps absorbing the dV/dt related gate voltage spike to a level lower than gate voltage threshold. It is one of the possible mitigation solutions available in the literature. After doing so, power efficiency has gone from 92% to 94.5%. I assume that it's best to test in a real life circuit to see if the problem exists and if the possible solutions behave as in the simulation. The reference document pdf describing the problem is https://toshiba.semicon-storage.com/info/docget.jsp?did=59473 (Mosfet self turn on phenomenon PDF) – rodv92 Feb 11 '22 at 16:43

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