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I've a small IP core module which performs some operations on a float input. The module has been developed using vivado hls. As shown below, the float input of the module is taken as a std_logic_vector.

entity basic_test is
port (
    ap_local_block : OUT STD_LOGIC;
    ap_local_deadlock : OUT STD_LOGIC;
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    input_r : IN STD_LOGIC_VECTOR (31 downto 0);
    output_r : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;

After the integration in vivado, the input to be connected to the module is actually a signed type. Assuming that i would like to avoid to make any cast inside the HLS IP core, which is the best strategy to make the conversion from signed to a float expressed in std_logic_vector?

Thanks in advance for your help.

Tony
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  • I would suggest using the IEEE fixed/float packages in VHDL-2008. However, last time I used Vivado (2018-2) I developed my whole core in -2008 only to find the IP packager didn't support a language standard that was only 10 years old. Check they fixed that ... or use the older ieee_proposed package. Alternatively, if you do decide to roll your own, it's just fiddling with bits. Trivial but tedious to get right if you need P754. –  Jan 27 '22 at 13:45
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    Tony, I've done this many times before. What's the difficulty? You should be able to just sit down with paper and pencil and work out what's needed. I used a barrel-shifter to shift bits in a single clock for the mantissa and to produce a shift count I used for the exponent. It's not that complicated. I don't see any of your thoughts or work above. Are you unable to come up with anything at all? – jonk Jan 27 '22 at 14:10

0 Answers0