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I'd like to execute a virtual sequence's task as below:

class MYTest extends uvm_test;                                                                      
  
  my_base_ahb_vseq_c my_base_ahb_vseq;                                                              
  
  `uvm_component_utils_begin(MYTest)                                                                
    `uvm_component_utils_end                                                                        
  
  function new(string name = "MYTest",uvm_component parent);                                        
    super.new(name,parent);                                                                         
  endfunction : new                                                                                 
  
  virtual function void build_phase(uvm_phase phase);                                               
    super.build_phase(phase); 
    my_base_ahb_vseq = my_base_ahb_vseq_c::type_id::create("my_base_ahb_vseq", this);                  
  endfunction : build_phase
  

  virtual function void end_of_elaboration_phase(uvm_phase phase);
        uvm_root uvm_top = uvm_root::get();
        super.end_of_elaboration_phase(phase);
        `uvm_info(get_type_name(), $sformatf("MYTest!!! \n %0s", uvm_top.sprint()), UVM_LOW)
  endfunction

   task run_phase(uvm_phase phase);                                                                               
        phase.raise_objection(this);
        `uvm_info(get_type_name(), "My AHB Test Start!!", UVM_LOW)                                                        
        my_base_ahb_vseq.do_write(8'h12, 8'h34);                                                     
        phase.drop_objection(this);                                                                                   
    endtask

I implemented the virtual sequence as below:

class my_base_ahb_vseq_c extends AhbUvmUserVirtualSeq;

    myAhbTransaction trans;
    
    `uvm_object_utils_begin(my_base_ahb_vseq_c)
      `uvm_field_object(trans, UVM_ALL_ON)
    `uvm_object_utils_end
    
    function new(string name="my_base_ahb_vseq_c");
        super.new(name);
    endfunction // new

 endclass

When I execute MYTest, I got the error message below:

xmsim: *E,TRNULLID: NULL pointer dereference.
          File: VirtualSeqLib.sv, line = 258, pos = 13
         Scope: pstest.my_base_ahb_vseq_c@3148_1.do_write
          Time: 0 FS + 33
Verilog Stack Trace:
0: task pstest.my_base_ahb_vseq_c@3148_1.do_write at ../VirtualSeqLib.sv:258
1: task pstest.MYTest@3049_1.run_phase at ../UserTest.sv:37

How do I execute the virtual sequence's task in the test class correctly?

Carter
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1 Answers1

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In general, the error message means that you declared an object but you did not construct the object before you tried to use it. A declared object defaults to the value null. You would construct an object using the new or create functions.

I assume line 258 is the following:

    `uvm_do_on_with(trans, p_sequencer.masterSeqr1, {

The message is not specific enough to determine which pointer is null: trans or p_sequencer.masterSeqr1. If we assume trans is null, you could try to construct it somewhere, such as in the constructor for the my_base_ahb_vseq_c class:

function new(string name="my_base_ahb_vseq_c");
    super.new(name);
    trans = new();
endfunction // new

Otherwise, the error likely is due to p_sequencer.masterSeqr1. In that case, you need to track down how you implemented the sequencer. It might be in your env class.


Note that 32'addr is a syntax error. It is surprising that your compiler accepts it. I don't think this is related to your reported error, but you should fix it. For example, change:

            FirstAddress == 32'addr;

to:

            FirstAddress == addr;

I notice your UVM sequence does not have a task named body. It is conventional to do so, and it is also conventional to call it from the test using the start function. Perhaps if you follow these conventions, you can more easily avoid errors of this type.

toolic
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