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I am working on a 2 layer board with ground and power layer on top and bottom and I have reached a single point where the 2 layers are limiting my design.

It is regarding SPI signals that would be working with 40MHz frequency communicating to a display. As shown in the top layer and bottom layer pictures.

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enter image description here

I have encountered the following problems:

  1. SCLK and SDA signals are on opposite pins between connector and MCU so I had to trace one of them behind the pin so as to avoid crossing each other

  2. This solution has caused my power(5V, 3V3) pins to be isolated between the SDA and SCLK signals and I am struggling on how to reach the power pins, on the connector, with a minimum EMI problems.

As you can see I've routed 5V and low speed signal underneath the SDA and SCLK pads so as to avoid crossing bellow SDA and SCLK traces. Still there is a small gap of 0.5mm(20mils) between the pads and the closest ground layer. However, when it comes to the 3V3 trace I really had to cross underneath the SCLK signal.

I was wondering if some of you experienced EMI professionals could tell me how serious of problem am I causing with this solution and is there any alternative approach that would be better?

Phill Donn
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    40MHz square waves on long traces with no plane is asking for trouble whether or not you have traces underneath. – DKNguyen Jan 21 '22 at 15:37
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    `I have reached a single point where the 2 layers are limiting my design` - go for a 4 layer board. – Andy aka Jan 21 '22 at 15:58
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    Your waveform travels in the dielectric between the ground plane and the signal trace even on a two layer board, it isn't just in the "signal" line. Running another trace under it means breaking half of the line, which will generate reflections and cross talk. You'd have to look at the whole length of that line and how sensitive it is to reflections to decide if that is ok or not. If the line is short and/or you can put the break very close to the source perhaps you could tolerate it. – user1850479 Jan 21 '22 at 16:04
  • @DKNguyen Are you saying "no plane" because my ground plane is too far away due to it being a 2 layer board? I am confused because I do have a ground plane underneath. The traces are 38mm(1.5inch), would you consider this long? – Phill Donn Jan 21 '22 at 16:23
  • @user1850479 Would you consider a 38mm(1.5inch) line between MCU and connector to be short or long for the 45 MHz? How would making the break closer to the source improve the situation. Is this because the reflections would be much smaller because the distance is much shorter than the wavelength of the travelling wave? – Phill Donn Jan 21 '22 at 16:32
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    @PhillDonn A plane is so longer a plane if you start cutting it up. – DKNguyen Jan 21 '22 at 16:34
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    I would never even consider starting a design with a 40 MHz clock on it on a 2 layer board. 4 layers would be the absolute minimum, and 6 would be better if the board has any size to it. – SteveSh Jan 21 '22 at 16:45
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    Read [this](https://electronics.stackexchange.com/questions/604828/routing-traces-to-and-from-a-48-pin-microcontroller-becoming-a-mess/604837#604837) answer for advice on 2-layer design. It implicitly says that you must have a ground running with your signals. 2 layer does not allow you planes, period. – Neil_UK Jan 21 '22 at 17:07
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    Assuming 0.6C for the signal, 45MHz has a wavelength of four meters. If we take 1/4 wavelength has being when things start to matter then it becomes 1m. But your 45MHz is a square wave, not a sine wave so has harmonics higher than that. If we go up to the 25th harmonic, then it becomes 4cm. Also, see how source termination works and why you place the resistor near the driver and what happens to those reflections. – DKNguyen Jan 21 '22 at 17:10

1 Answers1

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Comments

  1. The frequency of crosstalk is not just the clock rate, but the bandwidth of the risetime. e.g. tr=1ns has -3dB BW of about 350 MHz. This risetime also depends on trace and load capacitance to ground with a wide tolerance on the source resistance of typically 35 Ohms for 3.6V logic such as ARM based uC.
  2. Get http://www.saturnpcb.com free software to compute trace capacitance and impedance, crosstalk for coplanar and microstrip/stripline enter image description here enter image description here
  3. Thinner dielectric layer is inverse to crosstalk with lower trace impedance to ground. So more layers helps reduce conductor gaps.
  4. Use microvias and more of them less than 15% of \$\lambda_{f_{-3dB}}\$ apart.
  5. Add 10:1 probe tip and gnd spring test points making the holes large enough to support the probe, such as 2nd photo above.
  6. Learn to estimate crosstalk and then learn how to validate this in your next design. There are many factors to learn.
  7. Find out more about highspeed PCB design from IPC-2251, normally a fee-based spec, but if you dig, you can find some things.
  8. Hire an expert in IPC-2251 to layout your next board. The skills you learn and success may be worth more than the cost of failure.
  9. Learn some new tools and learn from datasheets how to model source impedance from Vol/Iol and C from rise time, then compute transmission lines from Saturn and Transmission Line Analysis in Falstad. Saturn gives voltage and dB crosstalk and it is important to know if the noise is coherent, edge-triggered or latched. If you have fee-based tools, perhaps better, but lots to learn.
    Below shows random length traces and different width/height ratio=impedance with vias shown (add 1.x nH) enter image description here enter image description here

Notice that I reduced the risetime at source and the dominant ringing matches the -3dB BW in Saturn near 350 MHz with 5ns /div.

  1. Reconsider item 8.
  2. Notice you can use the mousewheel in Falstad to change the load to 100 Ohms and get almost a textbook waveform at 2.5V from 3.3
Tony Stewart EE75
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