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I was reading a paper regarding fault detection in combinational logic circuits and read something that I do not understand. It is about the downsizing of transistors making them more prone to hard faults.

It says: "Generally, in new generation technologies, we have less reliability than in the old ones. Some of the reasons for these problems are: lower CL (load capacitance), lower VDD or VCC (supply voltage) that lead to a smaller noise margin, lower Q Critical, more process variation [4] and manufacturing defects[5]".

How is lower load capacitance caused by the transistors' getting smaller? Is total input capacitance for the FET not increased with the smaller PN junction gap?

Paper Link

ocrdu
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David777
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2 Answers2

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The load capacitance in CMOS logic circuits mainly consists of the capacitance between the gate and the substrate (often called Bulk) \$C_{GB}\$.

In newer technologies the gate area (length x width) generally gets smaller making the gate capacitance \$C_{GB}\$ smaller as well. That's because this capacitance is simply a capacitance per area. So more area means more capacitance.

Is total input capacitance for the FET not increased with the smaller PN junction gap?

The only PN junctions that are involved are the drain to substrate and source to substrate capacitances \$C_{DB}\$, \$C_{SB}\$. Remember that in CMOS logic circuits, MOSFETs are used, not JFETs. These substrate capacitances are directly related to the width of the transistors. In newer technologies, the width generally gets smaller and that makes these capacitances smaller as well (assuming the doping levels in the PN junctions don't change drastically, which usually they don't).

I don't know what you mean by "PN junction gap", my guess is that you mean the depletion region? The size of the depletion region does mainly depends on doping levels and applied voltages. If we kept those the same between technologies, the size of the depletion region would not change and the \$C_{DB}\$, \$C_{SB}\$ capacitances would stay the same if we kept them the same size. However, in newer techologies, they can be made smaller in size as the transistors can be made smaller.

Bimpelrekkie
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  • Right ok, that makes sense. It is actually the surface area dictates capacitance more so that the gap. But why does a smaller area and less capacitance make the transistor more fault prone? – David777 Jan 13 '22 at 13:12
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    *But why does a smaller area and less capacitance make the transistor more fault prone?* Faults and resulting yield (how many ICs on a wafer are damaged) is a complex subject! You could say that smaller transistors can be damaged by smaller particles that would not affect a larger transistor. So in manufacturing, for smaller transistors, you will need a "cleaner' environment to get rid of those smaller particles. If you didn't do that then smaller transistors would be more fault prone. – Bimpelrekkie Jan 13 '22 at 13:16
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    I'm not sure I agree with the article's "*Generally, in new generation technologies, we have less reliability than in the old ones*" If that were true then how can TSMC for example get good enough yield (high enough reliability) on 7 nm processes? There are things that can be done to increase the reliability of small transistors: a cleaner fabrication environment. So that's what TSMC provides. Given the same environment, then yes, smaller transistors are less reliable. But change the environment and you can get the reliability back. – Bimpelrekkie Jan 13 '22 at 13:22
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Is total input capacitance for the FET not increased with the smaller PN junction gap?

No, it becomes smaller because, for a parallel plate capacitor (simple example): -

$$C = \epsilon\times\dfrac{\text{Area}}{\text{gap between plates}}$$

Given that area is proportional to distance squared then area reduces faster that the gap dimension when things are scaled down.

How is lower load capacitance caused by the transistors' getting smaller?

This probably refers to when a second gate is connected to an output of a gate. The second gate's input capacitance drops with scale as shown above.

Andy aka
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  • Ah I see, but how does lower gate capacitance make the transistor more fault prone? – David777 Jan 13 '22 at 13:12
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    @David777 noise can be regarded as an occurrence of charge injection. If the "capacitor" needs less charge to convert its voltage from logic 0 to logic 1 then it's more prone to become in error when noise is present. Particularly so in modern memory chips that store a 1 or a 0 as voltage on a capacitor. It's a poorly written article IMHO and I don't necessarily agree with any of the points it makes. – Andy aka Jan 13 '22 at 13:28