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When using an open drain communication scheme, like I2C, it seems that the majority of power consumption comes from the sinking of current through the pull up resistor when a logic 0 is transmitted.

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My question is: is there any power consumption when transmitting a logic 1, or do we only consume power when transmitting 0s? My guess is that there will need to be some current drawn when sending a 1 to charge the internal capacitances of the downstream receiver, but it will be significantly less current consumption than when we try to transmit a 0.

Jake Hertz
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3 Answers3

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Yes there will be. If you purely concentrate on this circuit (and not that which drives the FET), there is a dynamic aspect and a static aspect

DYNAMIC

When the state changes from 0 to 1, there will a pulse of power draw due to three routes

  1. switching loss in the FET as it is turned off
  2. charging the transmission line
  3. charging current as the pull-up resistor charges the receiving end load capacitance

STATIC

With a steady "1" being transmitted there is always going to be some leakage current.

  1. The transmitting FET will have an OFF resistance that does not equal infinity.

  2. The receiving buffer will have an input resistance that does not equal infinity.

  3. There is also dielectric leakage associated with what the signal is being transmitted over (FR4, Polyimide, harness).

These are typically extremely low, and more of a theoretical concern rather than a power supply sizing concern.

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My guess is that there will need to be some current drawn when sending a 1 to charge the internal capacitances of the downstream receiver, but it will be significantly less current consumption than when we try to transmit a 0.

Yes, when you transmit a 1 after transmitting a 0, capacitances need to be charged, and that power is used. But if you transmit a 1 after another 1, then the capacitance is already charged, so the circuit just burns the input leakage current of all the chips connected to it, which is usually very low.

In some cases it is possible to use an active pullup to cheat with the current. I've used it on 1wire. This would probably not work with I2C:

When the micro drives the wire, for a 0 to 1 transition, it switches its pin from open drain to push-pull to quickly drive the wire to a high level. When it is the device's turn to drive the wire, the micro switches in a low value pullup resistor just at the right time for a few µs to drive the wire high, then checks if the wire was actually driven high (if it was not, it means the device is driving it low).

bobflux
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  • A device on I2C bus should never actively drive the bus strongly high. Not even for rise time acceleration.That is a sure way to get more problems than solving them, as witnessed here by people who are asking why generic logic level shifting chips with rise and/or fall time accelerators cause their I2C bus to not work. – Justme Jan 01 '22 at 16:27
  • I used it on 1wire bus, it works fine, it suits the protocol well. Wouldn't use it on I2C, but then again, I2C isn't supposed to be misused with extra long wires... You're right I should have mentioned it was 1wire. – bobflux Jan 01 '22 at 17:02
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When the bus line has already reached high level, any capacitance, such as input or just stray capacitance has been charged so there is virtually no current flowing.

In practice all IO pins have some leakage currents but in general this is so small in modern CMOS chips that for any practical purposes with any practical pull-up resistance this can just be ignored.

Justme
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