Explain me please, how biasing exactly works here?
From my view, on positive half of signal, we need about 0,7V + signal voltage (let's say signal is 1V) on NPN base, relative to its emitter=relative to Gnd here. That's simple and clear. I can't figure out, what happens on negative half of signal.
I think, here C1 becomes like Vcc for PNP transistor, so we need Vcc-0,7-1V on its base to drive it open. But how it is possible to get at same time with same biasing circuit 1,7V on upper base AND Vcc-1,7V on lower base?