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I am trying to represent the combinational logic circuit to perform 5x3 multiplier operation using 1-bit full adder using CSEDAR Simulator, the label is based on this operations: enter image description here

My answer is as below, but the problem is that some operations work correctly like (11101 * 101) while others like (11001 * 111), can anyone tell me what's wrong with it? enter image description here

Amida
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  • It seems that one adder (which output T2)has no CI input ? – Antonio51 Dec 13 '21 at 13:20
  • Amida, I've already discussed it [here](https://electronics.stackexchange.com/a/258106/38098). Did you do any searches on this site? You can also compare a [standard and Wallace design for 4 bits](https://i.stack.imgur.com/H9vV6.png), too. – jonk Dec 13 '21 at 18:45

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Each row of your multiplier always needs 5 adders and carry signals must never propagate between rows, they may only go from right to left within a row. Carry-in of the adder producing T3 should be connected to ground. Insert another adder in the "N5" trace; connect the carry-out from "M5+N4" to it (instead of to T3).

Jonathan S.
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